Reconfigurable Arithmetic Circuit for Parallel Low-Latency Computing
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Solution Overview
Problem
Existing computing systems face limitations in computation speed and energy efficiency for mathematically intensive applications such as artificial intelligence, neural networks, digital currencies, and blockchain, with high energy consumption and heat dissipation issues.
Innovation Solution
A reconfigurable processor architecture with an array of fractal cores, featuring a reconfigurable arithmetic engine that includes input reordering queues, a multiplier shifter and combiner network, an accumulator circuit, and control logic, allowing for scalable, low-latency, energy-efficient processing of streaming data in real-time, capable of massively parallel computations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If existing computing systems are used for mathematically intensive applications, then computation processing is performed, but computation speed is insufficient and energy consumption is excessive
Solution Approach 1:
The computing system is divided into multiple independent computational cores that can operate in parallel. Each core is a self-contained unit capable of performing mathematical operations independently, allowing the system to process multiple tasks simultaneously and improve overall computation speed while distributing energy consumption across multiple units.
Solution Approach 2:
The system employs reconfigurable computational cores that can dynamically change their operational characteristics based on the specific computational task. This reconfigurability allows the hardware to be optimized for different types of mathematical operations, improving computation speed for specific applications while reducing energy consumption by activating only the necessary computational units.
2Productivity
If computational cores are scaled up to increase processing capability, then computation performance improves, but heat dissipation increases
Solution Approach 1:
The system divides computational work across multiple segmented cores rather than using a single large processor. This segmentation distributes the heat generation across multiple smaller units, improving heat dissipation efficiency while maintaining high computation performance through parallel processing.
Solution Approach 2:
The system employs periodic activation and deactivation of computational cores based on workload demands. Not all cores operate continuously, which reduces average heat dissipation while maintaining high performance when needed through selective activation of required computational units.
3Productivity
If hardware is optimized for specific applications, then computation efficiency improves, but adaptability to other applications decreases
Solution Approach 1:
The computational cores are designed with universal functionality, capable of performing multiple types of mathematical operations including neural network computations, digital signal processing, encryption, and other mathematically intensive tasks. This multi-functionality allows the same hardware to be efficiently configured for different applications, maintaining both computation efficiency and adaptability.
Solution Approach 2:
The system uses dynamically reconfigurable hardware that can change its operational mode based on the required application. This reconfigurability allows the computational cores to be optimized for specific tasks when needed while maintaining the ability to adapt to other applications, resolving the trade-off between specialization and versatility.
Data Source
AI summary
A representative reconfigurable processing circuit and a reconfigurable arithmetic circuit are disclosed, each of which may include input reordering queues; a multiplier shifter and combiner network coupled to the input reordering queues; an accumulator circuit; and a control logic circuit, along with a processor and various interconnection networks. A representative reconfigurable arithmetic circuit has a plurality of operating modes, such as floating point and integer arithmetic modes, logical manipulation modes, Boolean logic, shift, rotate, conditional operations, and format conversion, and is configurable for a wide variety of multiplication modes. Dedicated routing connecting multiplier adder trees allows multiple reconfigurable arithmetic circuits to be reconfigurably combined, in pair or quad configurations, for larger adders, complex multiplies and general sum of products use, for example.