Reconfigurable Arithmetic Core Architecture for Parallel Low-Latency Computing

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Solution Overview

Problem

Existing computing systems face limitations in computation speed, energy efficiency, and heat dissipation, particularly for mathematically intensive applications such as artificial intelligence, neural networks, and blockchain, with a need for scalable, low-latency, and energy-efficient computing architectures capable of real-time processing and massively parallel operations.

Innovation Solution

A reconfigurable processor architecture featuring an array of computational cores with reconfigurable arithmetic engines, including input reordering queues, multiplier shifters, accumulators, and control logic circuits, allowing for scalable, energy-efficient, and low-latency processing of streaming data, supporting various applications like AI, neural networks, and blockchain.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If existing computing systems are used for mathematically intensive applications, then computation processing is performed, but computation speed is insufficient and energy consumption is excessive

Engineering Contradiction:

Improvecomputation speedVSAvoidenergy consumption

Core Design Contradiction:

SpeedVSUse of energy by moving object

Solution Approach 1:

The computing system is divided into multiple independent computational cores that can operate in parallel. Each core is a self-contained unit capable of performing computations independently, allowing the system to process multiple mathematical operations simultaneously, thereby increasing overall computation speed while distributing energy consumption across multiple units.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The architecture employs reconfigurable computational cores that can dynamically change their operational characteristics based on the specific computational task. This dynamic reconfiguration allows the system to optimize its structure and resource allocation for different mathematical intensive applications, improving computation speed while minimizing energy consumption by activating only the necessary computational resources.

Inventive Principle:

Principle #15Dynamics

2Productivity

If existing computing systems are used for mathematically intensive applications, then computation is performed, but heat dissipation is excessive

Engineering Contradiction:

Improvecomputation capabilityVSAvoidheat dissipation

Core Design Contradiction:

ProductivityVSTemperature

Solution Approach 1:

By segmenting the computing system into multiple distributed computational cores, the heat generation is spread across multiple physical locations rather than concentrated in a single processor. This spatial distribution of computational workloads reduces the thermal density at any given point, thereby managing heat dissipation more effectively while maintaining high overall computation capability.

Inventive Principle:

Principle #1Segmentation

3Use of energy by moving object

If computing architecture is made reconfigurable to optimize for specific applications, then energy efficiency is improved, but device complexity increases

Engineering Contradiction:

Improveenergy efficiencyVSAvoidarchitecture complexity

Core Design Contradiction:

Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The computational cores are designed with universal reconfigurable capabilities that allow them to perform multiple different computational functions by changing their internal configuration. This multi-functionality enables the same hardware structure to be optimized for various mathematical intensive applications (such as neural networks, blockchain, FFTs) without requiring entirely different architectures, thereby improving energy efficiency across diverse workloads while limiting the increase in device complexity through standardized core designs.

Inventive Principle:

Principle #6Universality (Multi-functionality)

4Speed

If massively parallel processing is implemented, then computation speed is improved, but device complexity increases

Engineering Contradiction:

Improvecomputation speedVSAvoidprocessing architecture complexity

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The system is segmented into multiple identical or similar computational cores that can be replicated and arranged in parallel configurations. This segmentation approach enables massively parallel processing by simply increasing the number of cores rather than creating increasingly complex single-core architectures, thereby improving computation speed while managing device complexity through modular replication of standardized core units.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS12461890B2Reconfigurable processor circuit architecture

Publication Date: 2025.11.04 CORNAMI INC

AI summary

A representative reconfigurable processing circuit and a reconfigurable arithmetic circuit are disclosed, each of which may include input reordering queues; a multiplier shifter and combiner network coupled to the input reordering queues; an accumulator circuit; and a control logic circuit, along with a processor and various interconnection networks. A representative reconfigurable arithmetic circuit has a plurality of operating modes, such as floating point and integer arithmetic modes, logical manipulation modes, Boolean logic, shift, rotate, conditional operations, and format conversion, and is configurable for a wide variety of multiplication modes. Dedicated routing connecting multiplier adder trees allows multiple reconfigurable arithmetic circuits to be reconfigurably combined, in pair or quad configurations, for larger adders, complex multiplies and general sum of products use, for example.