Reconfigurable Arithmetic Circuit for Parallel Low-Latency Compute
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Solution Overview
Problem
Existing computing systems face limitations in processing speed and energy efficiency for mathematically intensive applications such as artificial intelligence, neural networks, digital currencies, and blockchain, leading to inadequate performance and high energy consumption.
Innovation Solution
A reconfigurable arithmetic engine circuit with a scalable architecture that includes input reordering queues, a multiplier shifter and combiner network, an accumulator circuit, and control logic circuits, allowing for configuration into various operating modes and interconnection networks to optimize performance for specific applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If existing computing systems are used for mathematically intensive applications, then computation processing is performed, but the speed of computation is insufficient and energy consumption is excessive
Solution Approach 1:
The computing system is divided into multiple computational cores that can operate in parallel. Each core is a self-contained unit capable of independent computation, allowing the system to process multiple mathematical operations simultaneously, thereby increasing overall computation speed while distributing energy consumption across multiple units
Solution Approach 2:
The computational cores are designed to be reconfigurable, allowing them to dynamically adapt their internal structure and operation mode based on the specific computational task at hand. This dynamic reconfiguration optimizes the balance between computation speed and energy consumption for different mathematical workloads
2Productivity
If computational cores are increased to improve processing capability, then computation performance improves, but device complexity increases
Solution Approach 1:
Each computational core is designed as a universal unit that can perform multiple types of mathematical operations (addition, multiplication, accumulation, etc.) through reconfiguration. This multi-functionality allows a smaller number of versatile cores to replace a larger number of specialized units, reducing overall system complexity while maintaining high computation capability
Solution Approach 2:
The system employs a hierarchical structure where computational cores are organized in a scalable array, with each core containing nested functional units (multipliers, adders, accumulators) that can be independently configured. This nested organization allows for systematic scaling and simplifies the management of complex multi-core systems
3Adaptability or versatility
If reconfigurable architecture is implemented to optimize for specific applications, then computing performance is optimized, but device complexity increases
Solution Approach 1:
The computational cores utilize configurable parameters such as operand width (e.g., 8-bit, 16-bit, 32-bit), operation type (addition, multiplication, accumulation), and data format (fixed-point, floating-point) to adapt to different applications. These parameter changes are achieved through control signals that reconfigure the internal circuitry without requiring physical hardware changes, balancing adaptability with implementation simplicity
Data Source
AI summary
A representative reconfigurable processing circuit and a reconfigurable arithmetic circuit are disclosed, each of which may include input reordering queues; a multiplier shifter and combiner network coupled to the input reordering queues; an accumulator circuit; and a control logic circuit, along with a processor and various interconnection networks. A representative reconfigurable arithmetic circuit has a plurality of operating modes, such as floating point and integer arithmetic modes, logical manipulation modes, Boolean logic, shift, rotate, conditional operations, and format conversion, and is configurable for a wide variety of multiplication modes. Dedicated routing connecting multiplier adder trees allows multiple reconfigurable arithmetic circuits to be reconfigurably combined, in pair or quad configurations, for larger adders, complex multiplies and general sum of products use, for example.