Reconfigurable Array Dynamic Mode Switching for Loop Execution
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Solution Overview
Problem
Reconfigurable architectures face challenges in efficiently executing loops due to the inflexibility of hardware processing and the slower speed of software processing, necessitating a method to dynamically select between Very Long Instruction Word (VLIW) and Coarse-Grained Array (CGA) modes based on loop characteristics.
Innovation Solution
An apparatus and method that acquires performance information to estimate execution times in both VLIW and CGA modes, generates corresponding codes, and determines the optimal execution mode by comparing the number of iterations or execution time estimates with a threshold intersection, allowing for dynamic mode switching to optimize loop execution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If hardware processing is used in reconfigurable architectures, then processing speed is improved, but flexibility and adaptability deteriorate
Solution Approach 1:
The reconfigurable architecture dynamically switches between VLIW mode and CGA mode based on loop characteristics. The system can reconfigure processing units and interconnect structures at runtime, allowing it to adapt its hardware configuration to match the specific requirements of different loop iterations, thus maintaining both high speed and flexibility
Solution Approach 2:
The system changes operational parameters by switching between two distinct execution modes: VLIW mode for loops with fewer iterations and CGA mode for loops with more iterations. This parameter change allows the architecture to optimize processing speed while maintaining adaptability to different computational workloads
2Adaptability or versatility
If software processing is used to provide flexibility, then adaptability is improved, but processing speed deteriorates
Solution Approach 1:
Rather than using slow software processing for all tasks, the system dynamically configures hardware structures to match the computational requirements. The reconfigurable interconnect and processing units are adjusted at runtime to provide software-like flexibility while maintaining hardware-level processing speed
Solution Approach 2:
The reconfigurable architecture serves multiple functions by being able to operate in both VLIW and CGA modes. The same hardware platform can handle different types of computational workloads efficiently, providing universal adaptability without sacrificing processing speed for any specific task type
3Productivity
If the reconfigurable architecture uses both VLIW and CGA modes, then loop execution efficiency is improved, but system complexity increases
Solution Approach 1:
The system segments loop execution into two distinct operational modes with clear boundaries. A mode determination unit analyzes loop characteristics and selects the appropriate execution mode, creating a segmented approach that improves efficiency while managing complexity through clear separation of execution paths
Solution Approach 2:
The mode determination unit performs preliminary analysis of loop characteristics before execution begins. By determining the appropriate mode (VLIW or CGA) in advance based on iteration count and other parameters, the system avoids runtime complexity while maximizing loop execution efficiency
Data Source
AI summary
An apparatus and method for dynamically determining the execution mode of a reconfigurable array are provided. Performance information of a loop may be obtained before and/or during the execution of the loop. The performance information may be used to determine whether to operate the apparatus in a very long instruction word (VLIW) mode or in a coarse grained array (CGA) mode.