Mapping Reconfigurable Array Vertices via Integer Linear Programming
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Solution Overview
Problem
Existing mapping methods for reconfigurable arrays result in poor operation performance with large initial intervals and low processing element utilization rates due to inefficient vertex and edge mapping on coarse-grained reconfigurable architectures.
Innovation Solution
A method involving the creation of an integer linear programming model to map processing vertices and edges within a data dependence graph onto a reconfigurable architecture, utilizing adjacency matrices to optimize the initial interval and achieve high resource utilization, involving steps such as obtaining a maximum time step and minimum initial interval, establishing constraints, and iteratively adjusting the initial interval until a valid mapping is found.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If existing mapping methods are used for reconfigurable arrays, then the mapping process is simple, but the operation performance is poor with large initial intervals and low PE utilization rates
Solution Approach 1:
The mapping process is segmented into distinct phases: data dependence graph analysis to determine TS_max and minimum initial interval, adjacency matrix construction for architecture representation, integer linear programming model formulation with specific constraints, and iterative solution processes. This segmentation allows each phase to be optimized independently while maintaining overall mapping effectiveness.
Solution Approach 2:
The method performs preliminary analysis of the data dependence graph before mapping to identify TS_max and minimum initial interval. Adjacency matrices are pre-constructed to represent processing element relationships. The integer linear programming model is pre-formulated with all necessary constraints, enabling systematic optimization rather than trial-and-error mapping approaches.
2Loss of time
If existing mapping methods are used, then the implementation is straightforward, but the initial interval is large and mapping efficiency is low
Solution Approach 1:
The method systematically varies the initial interval parameter starting from the minimum value determined during graph analysis. The integer linear programming model incorporates the initial interval as a key parameter that is iteratively adjusted. By changing this parameter and re-solving the optimization model, the method finds the optimal initial interval that minimizes time loss while maintaining high mapping efficiency.
Solution Approach 2:
The mapping process incorporates feedback through the iterative solution of the integer linear programming model. The model evaluates whether a valid mapping exists for the current initial interval, and if not, the interval is adjusted and the model is re-solved. This feedback loop continues until an optimal mapping is found, ensuring minimal initial interval while maintaining correctness.
3Productivity
If the reconfigurable architecture is optimized for high PE utilization, then the mapping complexity increases due to multiple constraints and iterative adjustments
Solution Approach 1:
The integer linear programming model serves multiple functions simultaneously: it enforces data dependence constraints, ensures valid PE mappings, optimizes initial interval selection, and maximizes resource utilization. The adjacency matrices provide a universal representation that works for different reconfigurable architecture configurations. This multi-functionality reduces the need for separate optimization procedures.
Solution Approach 2:
The mapping approach is dynamic rather than static. The initial interval is not fixed but is iteratively adjusted based on the solution status of the integer linear programming model. The mapping process adapts to the specific characteristics of the data dependence graph and architecture configuration, dynamically finding the optimal parameters rather than using predetermined fixed values.
Data Source
AI summary
A mapping method for a reconfigurable array, including: Si obtaining and analyzing a DDG; providing an initial interval; obtaining a reconfigurable architecture; copying the first adjacency matrix and the second adjacency matrix to form a mapping space; establishing an integer linear programming model, and mapping, with the integer linear programming model, a processing vertex, an intra-cycle edge, and an inter-cycle edge in the DDG, to the mapping space, respectively; obtaining a mapping relationship from the processing vertex and the edge in the DDG to the processing element and the link of extended TS_max layers; and generating configuration information by the mapping relationship modulo the initial interval.