Reconfigurable Array Processor Floating-Point Operations
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Solution Overview
Problem
Current digital information processing technologies face challenges in efficiently performing floating-point operations, particularly in mobile multimedia platforms, where they require high performance and low power consumption while dealing with complex data processing and limited hardware resources.
Innovation Solution
A reconfigurable array processor with an array of processing elements connected in groups to perform floating-point operations, utilizing a configuration cache for controlling arithmetic operations and data communications, and a frame buffer for storing interim results, allowing for flexible configuration and efficient data processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If processing elements are connected in groups to perform floating-point operations, then floating-point operation capability is improved, but device complexity increases
Solution Approach 1:
The processor is divided into multiple processing elements (PEs) that can be independently configured. Each PE contains basic arithmetic logic units that can be grouped in different configurations (e.g., pairs of PEs) to perform floating-point operations, allowing the system to achieve floating-point capability through modular segmentation rather than requiring a completely complex dedicated floating-point unit
Solution Approach 2:
The processor employs dynamic reconfiguration capability where processing elements can be selectively connected and disconnected based on operational requirements. The system can switch between integer arithmetic mode (individual PEs operating independently) and floating-point operation mode (PEs connected in groups), allowing the device complexity to be managed dynamically rather than being permanently high
2Adaptability or versatility
If reconfigurable array is used for both integer and floating-point operations, then adaptability is improved, but manufacturing precision requirements increase
Solution Approach 1:
The same processing elements and interconnection structures are designed to serve multiple functions - both integer arithmetic operations and floating-point operations. The basic PE unit is universally applicable, and by changing the connection configuration (via configuration cache), the same hardware performs different arithmetic types, eliminating the need for separate dedicated hardware for each operation type and reducing manufacturing precision requirements
Solution Approach 2:
The system changes operational parameters (connection configurations, data formats, operation modes) rather than changing the physical hardware structure to support different arithmetic operations. The configuration cache stores different parameter sets that define how PEs should be connected and operated for integer vs. floating-point modes, allowing flexible adaptation without requiring high-precision manufacturing of multiple hardware variants
Data Source
AI summary
A processor for performing floating-point operations includes an array of processing elements arranged to enable a floating-point operation. Each processing element includes an arithmetic logic unit to receive two input values and perform integer arithmetic on the received input values. The processing elements in the array are connected together in groups of two or more processing elements to enable floating-point operation.