Reconfigurable Baseband ASIC for RF Block Coding

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Solution Overview

Problem

Conventional RF systems require multiple individual devices or circuits for performing multiple RF functions, which are expensive, power-intensive, and lack scalability and flexibility, with existing solutions like FPGAs and ASICs being costly and inflexible.

Innovation Solution

A radio frequency (RF) system incorporating a baseband engine ASIC with a memory, state machine, and programmable processing circuit that allows selection of programming instructions for performing various baseband engine operations, including block coding computations, and includes a channelization circuit and converters, enabling flexible operation across different RF functions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple individual devices or circuits are used to perform multiple RF functions, then functional versatility is improved, but device complexity, cost, and power consumption increase

Engineering Contradiction:

Improvefunctional versatilityVSAvoiddevice complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements a single reconfigurable device that can perform multiple RF functions including FFT, IFFT, FHT, Viterbi decoding, and CRC computations. The device uses a unified architecture with configurable processing elements that can be programmed to execute different algorithms, eliminating the need for multiple dedicated devices while maintaining full functional versatility

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent combines multiple previously separate RF processing functions into a single integrated device. The reconfigurable architecture merges FFT processing, Viterbi decoding, CRC computation, and other RF functions into one unified platform, reducing overall system complexity while preserving all required functionalities

Inventive Principle:

Principle #5Merging (Combining)

2Adaptability or versatility

If FPGAs are used to implement reconfigurable logic, then adaptability is improved, but cost and power demand increase

Engineering Contradiction:

ImprovereconfigurabilityVSAvoidpower demand

Core Design Contradiction:

Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

The patent changes the operational parameters of the processing elements to optimize for lower power consumption. The reconfigurable device uses configurable processing elements that can be programmed with specific algorithms, allowing the system to use only the necessary computational resources for each task rather than operating at full capacity, thereby reducing power demand while maintaining adaptability

Inventive Principle:

Principle #35Parameter changes

3Adaptability or versatility

If FPGAs are used to implement reconfigurable logic, then adaptability is improved, but manufacturing cost increases

Engineering Contradiction:

ImprovereconfigurabilityVSAvoidmanufacturing cost

Core Design Contradiction:

Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The patent implements a universal reconfigurable device that can perform multiple RF functions including FFT, IFFT, FHT, Viterbi decoding, and CRC computations. The device uses a unified architecture with configurable processing elements that can be programmed to execute different algorithms, eliminating the need for multiple dedicated devices while maintaining full functional versatility

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent uses a standardized reconfigurable architecture that can be replicated and programmed with different algorithms. The configurable processing elements can be programmed to copy and execute various RF processing functions, allowing a single device design to replace multiple specialized devices at lower cost

Inventive Principle:

Principle #26Copying

4Adaptability or versatility

If a programmable processing circuit is used to perform multiple block coding computations, then adaptability is improved, but device complexity increases

Engineering Contradiction:

Improvecomputational flexibilityVSAvoidcircuit complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent divides the reconfigurable device into multiple configurable processing elements that can be independently programmed. Each processing element can be configured to perform specific block coding computations such as CRC calculations or Viterbi decoding, allowing the system to achieve computational flexibility through modular segmentation rather than a monolithic complex circuit

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS11502715B2Radio frequency (RF) system including programmable processing circuit performing block coding computations and related methods

Publication Date: 2022.11.15 EAGLE TECHNOLOGY LLC

AI summary

A radio frequency (RF) system may include an RF transceiver and a baseband engine, application specific integrated circuit (ASIC) coupled to the RF transceiver and configured to perform a given baseband engine operation from among different baseband engine operations. The baseband engine ASIC may include a memory and a state machine coupled thereto and configured to store a respective set of programming instructions for each of different baseband engine operations and to permit selection of the given set of programming instructions. The baseband engine may also include a programmable processing circuit coupled to the memory and the state machine and configured to perform block coding computations responsive to the given set of programming instructions.