Reconfigurable Cache Bins for Low-Latency Coherent Access

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Solution Overview

Problem

Conventional cache coherence mechanisms in shared memory multi-core processors suffer from inefficiencies due to static pipeline operations and high latency, especially in reconfigurable cache architectures that do not improve memory access latency.

Innovation Solution

A reconfigurable cache architecture that dynamically partitions cache nodes into bins based on access parameters, using deterministic functions like hash functions to determine target cache bins, ensuring cache coherency without additional dedicated hardware, thereby reducing latency and improving memory access efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a conventional static pipeline cache coherence mechanism is used, then cache coherence can be maintained, but memory access latency is high and system performance is reduced

Engineering Contradiction:

Improvememory access latencyVSAvoidprocessing time in pipeline

Core Design Contradiction:

SpeedVSLoss of time

Solution Approach 1:

The patent implements dynamic cache partitioning where cache nodes are reconfigured into different bin configurations based on runtime access patterns. The system transitions from a static pipeline architecture to a dynamic reconfigurable architecture that adapts cache structure during operation, allowing optimal cache bin configurations to be selected based on actual workload characteristics, thereby reducing memory access latency while maintaining coherence

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The system changes the parameter of cache bin configuration dynamically. Different bin configurations (e.g., number of bins, bin sizes) are selected based on access patterns and workload characteristics. This parameter change allows the cache coherence mechanism to optimize for speed in certain configurations while reducing processing time in others, resolving the contradiction between maintaining coherence and achieving high performance

Inventive Principle:

Principle #35Parameter changes

2Use of energy by moving object

If direct addressing mapping is used for power reduction, then energy consumption is reduced, but memory access latency is not improved

Engineering Contradiction:

Improvepower consumptionVSAvoidmemory access latency

Core Design Contradiction:

Use of energy by moving objectVSSpeed

Solution Approach 1:

The patent segments the cache into multiple bin configurations that can be independently managed. By segmenting the cache structure and allowing dynamic reconfiguration of bins, the system can select configurations that optimize for low power consumption while simultaneously achieving low latency through intelligent bin selection based on access patterns, rather than using a single static direct addressing mapping scheme

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS20250335358A1Reconfigurable cache architecture and methods for cache coherency

Publication Date: 2025.10.30 NEXTSILICON LTD

AI summary

A method for cache coherency in a reconfigurable cache architecture is provided. The method includes receiving a memory access command, wherein the memory access command includes at least an address of a memory to access; determining at least one access parameter based on the memory access command; and determining a target cache bin for serving the memory access command based in part on the at least one access parameter and the address.