Reconfigurable Cache Memory Switching SRAM and MRAM
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Solution Overview
Problem
The performance enhancement of arithmetic cores is hindered by memory access time and power consumption, with existing cache memory solutions facing challenges in achieving high integration, cost-effectiveness, and balancing access speed and power efficiency.
Innovation Solution
A memory system with a reconfigurable cache memory that switches between a volatile SRAM-based L2 cache and a non-volatile MRAM-based L3 cache, using a hybrid mode to optimize access speed and power consumption by dynamically adjusting the cache configuration based on access frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If SRAM is used as cache memory to achieve high access speed, then access speed is improved, but integration difficulty and cost increase
Solution Approach 1:
The patent implements a reconfigurable cache memory system that dynamically switches between SRAM and MRAM based on access patterns. The cache controller monitors access frequencies and reconfigures the cache structure accordingly, using SRAM for frequently accessed data and MRAM for less frequently accessed data, thereby optimizing both speed and integration
Solution Approach 2:
The system changes the operational parameters of the cache memory by switching between different memory types (SRAM and MRAM) based on access frequency thresholds. This parameter change allows the system to adapt to different workload requirements, using high-speed SRAM when speed is critical and low-power, high-integration MRAM when cost and integration are priorities
2Speed
If SRAM is used as cache memory to achieve high access speed, then access speed is improved, but cost increases
Solution Approach 1:
The reconfigurable cache memory dynamically adjusts its composition based on access patterns. When access frequency is high, the system uses SRAM to maintain high speed performance. When access frequency is low, the system transitions to MRAM to reduce cost, thereby optimizing the cost-performance tradeoff dynamically
Solution Approach 2:
The system changes the memory type parameter based on access frequency thresholds. By monitoring access patterns and switching between SRAM and MRAM, the system adapts its cost structure to match actual performance requirements, reducing overall system cost while maintaining necessary speed performance
3Ease of manufacture
If MRAM is used as cache memory to achieve high integration and low power consumption, then integration and power saving are improved, but access speed decreases
Solution Approach 1:
The patent implements a dynamic reconfiguration mechanism where the cache controller monitors access frequencies and switches between MRAM and SRAM modes. For frequently accessed data, the system uses SRAM to compensate for MRAM's slower speed, while using MRAM for less frequently accessed data to maintain high integration and low power consumption
Solution Approach 2:
The system changes the operational mode parameter based on access frequency thresholds. When access frequency exceeds a threshold, the system switches to SRAM mode to improve speed. When access frequency is below the threshold, the system uses MRAM mode to maximize integration and power efficiency, thereby adapting to different performance requirements
4Use of energy by stationary object
If MRAM is used as cache memory to achieve low leakage power, then power consumption is reduced, but access speed decreases
Solution Approach 1:
The reconfigurable cache memory system dynamically switches between MRAM and SRAM based on access patterns. For frequently accessed data where speed is critical, the system uses SRAM. For less frequently accessed data where power saving is more important, the system uses MRAM, thereby optimizing the power-speed tradeoff dynamically
Solution Approach 2:
The system changes the memory type parameter based on access frequency thresholds. By monitoring access patterns and switching between MRAM and SRAM, the system adapts its power consumption to match actual performance requirements, reducing overall power usage while maintaining necessary speed performance
Data Source
AI summary
A memory system has a first cache memory comprising a volatile memory, a second cache memory comprising a non-volatile memory with access speed slower than access speed of the volatile memory, and a reconfiguration control circuitry to switch between a first mode that uses the second cache memory as a cache memory in a lower layer than the first cache memory and a second mode that uses the first cache memory and the second cache memory as cache memories in an identical memory layer.