Reconfigurable Logic Chip Offloads Host Processing Overhead
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Solution Overview
Problem
Conventional storage systems face overhead challenges due to dedicated hardware accelerators that do not efficiently manage data processing, leading to reduced processing speed and increased workload for the host.
Innovation Solution
A storage device set comprising a storage device and a reconfigurable logic chip, where the reconfigurable logic chip, such as an FPGA, processes encrypted data to reduce host overhead by performing calculations typically handled by the host, enabling secure communication and dynamic configuration for various applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a dedicated hardware accelerator is used to assist calculations, then processing speed is improved, but device complexity increases and host overhead increases
Solution Approach 1:
The patent applies universality by implementing a reconfigurable logic chip that can be dynamically configured to perform different calculation tasks. Instead of using dedicated hardware accelerators for specific functions, the system uses a single reconfigurable chip that can adapt to various computational requirements through configuration data, thereby reducing device complexity while maintaining processing speed improvements.
Solution Approach 2:
The patent applies dynamics by making the logic chip reconfigurable rather than static. The logic chip can change its functional configuration based on the calculation tasks required, allowing the system to optimize processing speed for different applications without adding permanent hardware complexity. This dynamic reconfiguration capability resolves the contradiction between speed improvement and device complexity.
2Speed
If a dedicated hardware accelerator is used to assist calculations, then processing speed is improved, but host overhead increases
Solution Approach 1:
The patent applies the intermediary principle by introducing a reconfigurable logic chip as a mediator between the host and the calculation tasks. The logic chip handles computational operations independently based on configuration data, reducing the burden on the host. This intermediary approach allows processing speed improvement while minimizing host overhead, as the host only needs to manage configuration data rather than direct calculation operations.
3Ease of operation
If a reconfigurable logic chip is used to reduce host overhead, then host overhead is reduced, but device complexity increases
Solution Approach 1:
The patent applies universality by designing a reconfigurable logic chip that can perform multiple calculation functions through configuration data. This multi-functionality reduces the need for multiple separate hardware components, thereby managing device complexity while achieving the goal of reducing host overhead. The single reconfigurable chip replaces what would otherwise require multiple dedicated accelerators or host processing capabilities.
4Reliability
If encryption is performed for secure data transmission, then security is improved, but processing speed decreases
Solution Approach 1:
The patent applies preliminary action by performing encryption operations as part of the data preparation process before data is processed or transmitted. The controller encrypts data in advance, allowing the reconfigurable logic chip to focus on computational tasks without additional encryption overhead during processing. This preliminary encryption approach maintains security while preserving processing speed for the main computational operations.
Data Source
AI summary
A storage device set includes a storage device configured to communicate with a host, the storage device including a controller configured to generate encrypted input data by encrypting data; and a reconfigurable logic chip configured to receive the encrypted input data from the storage device, generate processed data by processing the encrypted input data according to a configuration, and generate encrypted output data by encrypting the processed data.