Reconfigurable Circuit Data Flow Graph Processing
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Solution Overview
Problem
Existing reconfigurable processors face inefficiencies in processing data flow graphs due to the need for extensive storage and processing of command data for branching and loop operations, leading to increased processing time and memory requirements.
Innovation Solution
A data flow graph processing method that divides programs into subprograms and generates data flow graphs representing dependency between operations, reducing the number of configuration data sets and optimizing memory usage and processing time by selecting relevant data flow graphs based on conditional branch results.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If command data is sequentially read from memory and supplied to ALU circuit to configure function, then the reconfigurable processor can execute operations, but the processing time is extended beyond necessary due to sequential processing requirement
Solution Approach 1:
The patent segments the program into multiple subprograms based on branching processes, allowing each subprogram to be converted into a separate data flow graph. This segmentation enables parallel processing of independent operation sequences, eliminating the sequential bottleneck in command execution while maintaining correct operational logic through structured subprogram division.
2Productivity
If command data for loop operations is stored multiple times in memory equal to loop count, then the loop operations can be executed, but the volume of command data increases significantly
Solution Approach 1:
The patent creates a universal data flow graph that represents loop operations once, with the graph capable of being executed multiple times through iterative processing control. Instead of storing duplicate command data for each loop iteration, the same data flow graph structure serves multiple execution cycles, reducing memory requirements while maintaining full loop functionality.
3Productivity
If all branch target operations are processed beforehand in reconfigurable circuit, then conditional determination can be made, but the circuit scale increases and power consumption rises due to processing unnecessary operations
Solution Approach 1:
The patent implements dynamic configuration where the reconfigurable circuit is programmed with data flow graphs corresponding to only the currently needed branch target operations. The system dynamically selects and loads appropriate subprograms based on runtime conditions, allowing the circuit scale to adapt to actual processing needs rather than accommodating all possible branch targets simultaneously, thus reducing both circuit complexity and power consumption.
Data Source
AI summary
A data flow graph processing method divides a program describing target operations into two or more subprograms and converts each of the two or more subprograms into a data flow graph (DFG) representing dependency in execution between operations carried out in sequence. Also generated is flow data indicating the order of execution of DFGs corresponding to respective subprograms. DFGs are converted into configuration data and the flow data is converted into control data.