Reconfigurable 3D Convolution Engine for Dynamic Resource Allocation
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Solution Overview
Problem
Conventional systems and methodologies face limitations in performing real-time convolution operations due to restricted computation power and high power usage, especially for 3D convolution operations, as they rely on fixed hardware resources like Field Programmable Gate Arrays (FPGA) and Application Specific Integrated Circuits (ASIC).
Innovation Solution
A reconfigurable convolution engine is introduced, utilizing available on-chip resources such as FPGA and ASIC, which allocates multiple instances to operate in parallel, each comprising computing blocks that perform convolution operations on feature maps, and aggregates outputs using a pipeline adder, allowing for efficient reuse of compute resources and adaptation to various kernel sizes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional systems use fixed hardware resources (FPGA and ASIC) to perform convolution operations, then the system maintains stable hardware architecture, but the computation power is limited and cannot perform real-time convolution operations
Solution Approach 1:
The patent implements a reconfigurable convolution engine that dynamically adjusts hardware resources based on kernel size requirements. The system can reconfigure the number and arrangement of compute units, memory structures, and data flow paths in real-time to match different convolution operation demands, enabling both high-speed computation and adaptability to various kernel sizes without requiring multiple fixed hardware designs
Solution Approach 2:
The reconfigurable convolution engine is designed as a universal hardware architecture that can perform multiple convolution operations with different kernel sizes (3x3, 5x5, 7x7, etc.) using the same physical hardware resources. The engine dynamically allocates and reconfigures its internal structures to handle various convolution tasks, making a single hardware unit capable of replacing multiple specialized fixed-function units
2Productivity
If conventional systems allocate more hardware resources to increase computation power for real-time convolution, then the processing speed improves, but the power consumption increases significantly
Solution Approach 1:
The system dynamically configures hardware resources based on the actual computation requirements of each convolution operation. For smaller kernel sizes, fewer compute units and smaller buffer memories are activated, reducing power consumption. For larger kernels, the system scales up the active resources accordingly. This dynamic adaptation ensures that power consumption is optimized to match the actual workload rather than running at maximum capacity continuously
Solution Approach 2:
The reconfigurable engine changes operational parameters such as the number of parallel compute units, memory buffer sizes, and data flow width based on kernel size. This parameter adaptation allows the system to achieve real-time processing for required kernel sizes while avoiding the excessive power consumption that would result from always operating at maximum configuration
3Adaptability or versatility
If conventional systems use fixed hardware configuration for specific kernel sizes, then the hardware design is simple, but the system cannot adapt to various kernel sizes and requires multiple hardware configurations
Solution Approach 1:
The convolution engine is divided into modular, reconfigurable segments including compute units, memory buffers, and data flow controllers. Each segment can be independently configured and scaled. The compute units are organized in arrays that can be dynamically sized, and memory structures can be reconfigured to match different kernel dimensions, allowing flexible adaptation to various kernel sizes through modular assembly rather than monolithic fixed design
Solution Approach 2:
The reconfigurable architecture employs nested structures where smaller functional units are contained within larger configurable blocks. Compute units are nested within processing arrays, which are nested within the overall engine structure. This nesting allows hierarchical reconfiguration where smaller kernel sizes utilize subsets of the available resources, and larger kernels activate more comprehensive nested structures, providing adaptability without requiring completely different hardware designs
Data Source
AI summary
Disclosed is a reconfigurable convolution engine for performing a convolution operation on an image. A data receiving module receives image data. A determination module determines a kernel size based on the image data, clock speed associated to the convolution engine and number of available on-chip resources. An allocation module allocates a plurality of instances based on the kernel size. Each instance of the plurality of instances further comprises a set of computing blocks operating concurrently. Each computing block is configured to perform convolution operation on the feature map of the image. An aggregation module aggregates the convolution output of each computing block for each instance of the plurality of instances to produce a convolution result for the image.