Reconfigurable CRC Circuit for Fast Multi-Polynomial Computation
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Solution Overview
Problem
The calculation of Cyclic Redundancy Codes (CRC) on large data streams is complex and requires efficient processing to balance complexity and speed, especially in high-speed communication links with varying standards and generator polynomials.
Innovation Solution
A circuit and method using a dynamically reconfigurable table with multiplication and division sub-tables, and multiplexers to generate CRC codes based on a reconfigurable generator polynomial, allowing on-the-fly updates and efficient computation of CRC codes by leveraging recursive properties and bit-to-bit exclusive-OR operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a reconfigurable generator polynomial is used to support multiple communication standards, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent implements dynamic reconfiguration of the generator polynomial by making the polynomial coefficients configurable through control signals. The circuit can switch between different generator polynomials dynamically, allowing adaptation to multiple communication standards without requiring multiple dedicated hardware circuits for each standard.
Solution Approach 2:
The CRC computation circuit is designed as a universal processor that can handle multiple communication standards (such as HDLC, ATM, Ethernet) through a single reconfigurable hardware structure. By making the generator polynomial configurable, one circuit performs multiple functions that would otherwise require separate dedicated circuits for each standard.
2Productivity
If dedicated hardware operators with pre-populated tables are used, then computation speed is improved, but manufacturing complexity increases
Solution Approach 1:
Instead of manufacturing separate hardware circuits for each communication standard, the patent uses dynamic reconfiguration where a single circuit can be programmed at runtime to support different standards. The generator polynomial coefficients are loaded dynamically based on the required standard, eliminating the need for complex manufacturing processes that would produce multiple dedicated hardware variants.
Data Source
AI summary
A circuit for generating an N-bit cyclic redundancy code of a k-bit digit d, the code based on a reconfigurable generator polynomial P of degree N, the circuit including a dynamic table comprising a multiplication sub-table storing products resulting from multiplication by the polynomial P of each element definable over k bits, in the order of the scalar values of the k-bit elements; a division sub-table storing quotients resulting from Euclidean division by the polynomial P of each k-bit element shifted by N bits to the left, in the order of the scalar values of the k-bit elements; and a group of first multiplexers, each multiplexer connected to be indexed by a respective cell of the division table to transmit the contents of a corresponding cell of the multiplication table to an output of the dynamic table, of same rank as the respective cell of the division table.