Reconfigurable Crypto-Processor with Variable-Width ALU
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Solution Overview
Problem
Current communication standards, such as Bluetooth and ZigBee, are vulnerable to 'man-in-the-middle' attacks, compromising the security of internet-connected devices by revealing cryptographic keys, particularly in sensitive applications like medical devices and wearable technology.
Innovation Solution
A reconfigurable cryptographic coprocessor system that includes an instruction memory for ARX instructions and mode control instructions, a programmable arithmetic logic unit, and a rotator, capable of processing variable-width words to execute secure cryptographic functions like hash algorithms and key generation, implemented in FPGA or ASIC formats for enhanced security in IoT systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If fixed-width cryptographic processors are used, then hardware area is reduced, but adaptability to different cryptographic standards is lost
Solution Approach 1:
The patent implements dynamic reconfigurability where the arithmetic logic unit can change its operational width (16-bit, 32-bit, 64-bit) based on the cryptographic standard being executed. Mode control instructions dynamically adjust the width of the ALU and associated components, allowing the same hardware to adapt to different cryptographic algorithms without physical reconfiguration.
Solution Approach 2:
The patent creates a universal cryptographic processor that can execute multiple cryptographic standards (AES, SHA, RSA, ECC) through a single reconfigurable hardware architecture. The arithmetic logic unit serves multiple functions by changing its operational parameters via mode control instructions, eliminating the need for separate dedicated hardware for each cryptographic standard.
2Adaptability or versatility
If reconfigurable width components are used, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent merges the width control functionality into the existing mode control instruction mechanism. The same control signals that select cryptographic algorithms also control the operational width of the arithmetic logic unit and rotator, consolidating control logic and reducing overall system complexity despite the added reconfigurability.
Solution Approach 2:
The patent changes the operational parameters (width) of the arithmetic logic unit and rotator based on mode control instructions. By using parameter changes rather than physical reconfiguration, the system achieves adaptability while maintaining a fixed hardware structure, thus limiting the increase in device complexity.
3Reliability
If cryptographic operations are performed on resource-constrained devices, then security is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic width adjustment where the arithmetic logic unit operates at the minimum necessary width for each cryptographic operation. This dynamic adaptation allows the processor to perform secure cryptographic operations while consuming only the necessary amount of power, avoiding the constant high power consumption of fixed-width processors.
Solution Approach 2:
The patent changes the operational parameters of the cryptographic processor to match the specific requirements of each cryptographic algorithm. By adjusting the width parameter dynamically, the system achieves security equivalent to dedicated processors while reducing power consumption through optimized resource utilization on resource-constrained devices.
Data Source
AI summary
The present disclosure relates to systems and methods that provide a reconfigurable cryptographic coprocessor. An example system includes an instruction memory configured to provide ARX instructions and mode control instructions. The system also includes an adjustable-width arithmetic logic unit, an adjustable-width rotator, and a coefficient memory. A bit width of the adjustable-width arithmetic logic unit and a bit width of the adjustable-width rotator are adjusted according to the mode control instructions. The coefficient memory is configured to provide variable-width words to the arithmetic logic unit and the rotator. The arithmetic logic unit and the rotator are configured to carry out the ARX instructions on the provided variable-width words. The systems and methods described herein could accelerate various applications, such as deep learning, by assigning one or more of the disclosed reconfigurable coprocessors to work as a central computation unit in a neural network.