Reconfigurable Data Processor for Wireless Standards
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Solution Overview
Problem
Current data processor architectures for wireless communications face a trade-off between high-speed processing and flexibility, with ASICs being inflexible and DSPs unable to sustain high data rates, limiting their adaptability to evolving wireless standards.
Innovation Solution
A data processor unit featuring multiple operation-execution units, a programmable controller, and a routing circuit arrangement that allows for flexible routing of data and instructions, enabling high-speed processing of complex operations while supporting multiple standards.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If ASIC is used for data processing, then processing speed is improved, but flexibility deteriorates
Solution Approach 1:
The patent implements a data processor unit that can perform multiple different operations (FFT, IFFT, arithmetic operations, logic operations) through a single reconfigurable architecture. The operation-execution units can be dynamically configured via control signals to execute different algorithms required by various wireless communication standards, thereby achieving multi-functionality without requiring separate dedicated hardware for each standard.
Solution Approach 2:
The patent employs dynamically reconfigurable operation-execution units that can change their operational mode based on control signals. The data routing circuit arrangements can be dynamically adjusted to route data differently depending on the required operation, and the programmable controller can be programmed with different instruction sets to adapt to emerging wireless standards, providing dynamic adaptability while maintaining high processing speed.
2Adaptability or versatility
If DSP is used for data processing, then flexibility is improved, but processing speed deteriorates
Solution Approach 1:
The patent divides the data processor into multiple parallel operation-execution units, each capable of performing specific operations. This segmentation allows simultaneous execution of multiple operations on different data streams, significantly increasing processing throughput while maintaining the flexibility of a programmable architecture. The parallel structure enables the processor to handle high data rates by processing multiple elements concurrently.
Solution Approach 2:
The patent merges the advantages of ASIC (high-speed dedicated hardware) and DSP (flexible programmability) by combining fixed-function operation-execution units with a programmable control unit. The operation-execution units provide hardware-accelerated performance for specific operations, while the programmable controller provides flexibility to adapt to different standards, creating a hybrid architecture that achieves both high speed and flexibility.
3Speed
If dedicated hardware is designed for specific application, then processing speed is improved, but adaptability to emerging standards deteriorates
Solution Approach 1:
The patent enables parameter changes in the operation-execution units through programmable control. The control unit can modify operational parameters such as transform size, window functions, and filtering characteristics dynamically. This allows the same hardware to be optimized for different wireless standards (e.g., 3G, 4G, 5G) by changing control parameters rather than redesigning the hardware, maintaining high processing speed while adapting to emerging standards.
Data Source
AI summary
A data processor unit includes at least two operation-execution units, each one adapted to receive input data, perform a respective operation on the input data and outputting output data resulting after applying said operation; the data processor unit further includes: a data storage unit including at least two individually-accessible memory devices adapted to store data; a programmable controller adapted to be programmed so as to execute a selected program; a first data routing circuit arrangement adapted to receive data from the at least two memory devices, from the programmable controller and from a second data routing circuit arrangement, and for selectively routing selected ones among the received data to the input of the operation-execution units; the second data routing circuit arrangement is adapted to receive the output data outputted by the operation-execution units and to selectively route the output data to the at least two memory devices, to the programmable controller, and to the first data routing circuit arrangement. The programmable controller is operatively coupled to the at least two operation-execution units, to the first and second data routing circuit arrangements, and to the at least two memory devices for controlling the operation thereof.