Runtime Reconfigurable Dataflow Processor for Low Power Vision
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Solution Overview
Problem
Current synthetic vision systems for applications like micro-robots, UAVs, and embedded vision systems face challenges in efficiently recognizing and categorizing objects due to high computational demands and power consumption, which existing GPUs and custom hardware architectures struggle to address effectively.
Innovation Solution
A dataflow processor with reconfigurable processing tiles and a multi-port memory access module, allowing for runtime configuration and parallel execution of operations, is designed to efficiently process image data and implement computer vision algorithms like convolutional networks, reducing power consumption and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If custom hardware architectures are developed to improve performance and power consumption, then computational efficiency is improved, but device complexity increases
Solution Approach 1:
The processor is divided into multiple processing tiles (first subset and second subset) that can be independently configured and operated. Each processing tile handles specific operations, allowing the system to achieve high computational efficiency through parallel processing while managing complexity by distributing functions across modular units.
Solution Approach 2:
The processing tiles are configured at runtime to perform configurable operations, allowing the hardware architecture to adapt dynamically to different computational tasks. This runtime reconfigurability enables the system to optimize performance for specific algorithms (like convolutional networks) without being locked into a fixed architecture, balancing efficiency gains with manageable complexity.
2Productivity
If multiple processing operations are executed in parallel to improve throughput, then productivity is improved, but device complexity increases
Solution Approach 1:
The processing operations are segmented into two subsets of processing tiles that execute in parallel. The first subset performs a first plurality of configurable operations while the second subset performs a second plurality of configurable operations simultaneously, achieving high throughput through structured parallelism without requiring a fully complex interconnected system.
Solution Approach 2:
Multiple processing tiles are merged into a unified processor system with shared memory access through the multi-port memory access module. This allows parallel operations to be coordinated efficiently through a common memory interface, achieving high throughput while avoiding the complexity of completely independent processing units.
3Productivity
If a multi-port memory access module provides simultaneous data access to multiple processing tiles, then productivity is improved, but device complexity increases
Solution Approach 1:
The multi-port memory access module serves as a universal interface that handles data access for multiple processing tiles simultaneously. This single multi-functional component provides efficient data sharing and access coordination without requiring separate memory interfaces for each processing tile, improving data access efficiency while containing complexity in a dedicated memory control unit.
Data Source
AI summary
A processor includes a plurality of processing tiles, wherein each tile is configured at runtime to perforin a configurable operation. A first subset of tiles are configured to perform in a pipeline a first plurality of configurable operations in parallel. A second subset of tiles are configured to perform a second plurality of configurable operations in parallel with the first plurality of configurable operations. The process also includes a multi-port memory access module operably connected to the plurality of tiles via a data bus configured to control access to a memory and to provide data to two or more processing tiles simultaneously. The processor also includes a controller operably connected to the plurality of tiles and the multi-port memory access module via a runtime bus. The processor configures the tiles and the multi-port memory access module to execute a computation.