Reconfigurable Datapath Architecture for Fine-Grained UDB Functions
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Solution Overview
Problem
Conventional programmable logic devices (PLDs) and field-programmable gate arrays (FPGAs) face challenges such as high power consumption and large silicon area, limiting their flexibility and efficiency in implementing complex electronic systems, especially when additional peripherals are required, and they offer only coarse-grained digital programmability with limited options.
Innovation Solution
The introduction of a Universal Digital Block (UDB) architecture with a dynamic configuration memory that allows for the combination of digital and analog blocks, enabling the implementation of various functions through a programmable interconnect and a system controller that dynamically loads configuration data into structural arithmetic elements, allowing for reconfiguration of datapath functions on a cycle-by-cycle basis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional PLDs and FPGAs are used to implement complex electronic systems with additional peripherals, then functional versatility is improved, but silicon area and power consumption increase significantly
Solution Approach 1:
The patent implements a universal digital block that can dynamically reconfigure to perform multiple different digital functions. A single block can be programmed to implement various arithmetic operations, logic functions, and peripheral functions through a configuration memory and programmable interconnect, replacing the need for multiple dedicated hardware components and thereby reducing silicon area while maintaining functional versatility.
Solution Approach 2:
The patent employs dynamic reconfiguration capability where the digital block can change its function during runtime. The configuration memory can be updated with new function definitions, and the programmable interconnect can dynamically reroute signals, allowing the same hardware structure to adapt to different functional requirements without physical reconfiguration, thus reducing the need for additional permanent hardware.
2Adaptability or versatility
If conventional PLDs and FPGAs are used to implement complex electronic systems with additional peripherals, then functional versatility is improved, but power consumption increases
Solution Approach 1:
By creating a universal digital block that can perform multiple functions through software configuration rather than requiring multiple dedicated hardware peripherals, the patent reduces the total number of active components in the system. Fewer active components mean lower overall power consumption while maintaining the ability to implement various peripheral functions as needed.
Solution Approach 2:
The patent uses a configuration memory to store function definitions and a programmable interconnect to replicate routing patterns dynamically. Instead of having permanent physical connections for each possible function, the system creates virtual copies of routing paths through programming, allowing the same physical hardware to serve multiple functional roles with minimal additional power overhead.
3Device complexity
If coarse grained digital programmability is used in PSoC architectures, then device complexity is reduced, but digital programmability precision is limited
Solution Approach 1:
The patent segments the digital block into fine-grained programmable elements including individual logic units, arithmetic units, and routing segments. Each segment can be independently configured through the configuration memory, allowing precise control over the function and connectivity of each small portion of the digital block, thereby achieving fine-grained programmability without overwhelming device complexity.
Solution Approach 2:
The patent introduces a configuration memory and control logic as intermediaries between the simple hardware structure and the desired complex functionality. The configuration memory stores detailed routing and function definitions that mediate between the basic building blocks and the final implemented function, enabling precise digital programmability while keeping the actual hardware structure relatively simple and manageable.
Data Source
AI summary
An apparatus includes a configuration memory coupled to one or more structural arithmetic elements, the configuration memory to store values that cause the structural arithmetic elements to perform various functions. The apparatus also includes a system controller to dynamically load the configuration memory with values, and to prompt the structural arithmetic elements to perform functions according to the values stored by the configuration memory.