Reconfigurable Delay Circuit for Short-Pulse Timing Adjustment
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Solution Overview
Problem
Existing delay circuits in integrated circuits face inefficiencies in adjusting signal timing due to inconsistent distances between output ports, leading to resource waste and process fluctuations when implementing short delays.
Innovation Solution
A delay circuit design with multiple sub-circuits connected through switch units, controlled by a central unit to adjust delay times by series or parallel connections, utilizing phase inverters and transistors to optimize delay processing and reduce resource waste.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple output ports are provided on a single delay chain with inconsistent distances, then different delay processing can be implemented, but resource waste and process fluctuations occur when implementing short delays
Solution Approach 1:
The delay chain is segmented into multiple independent delay sub-circuits, each capable of being independently activated. This allows only the necessary sub-circuits to be used for the required delay time, avoiding resource waste from using the entire delay chain for short delays.
Solution Approach 2:
The circuit dynamically reconfigures its structure by connecting delay sub-circuits in series or parallel based on the required delay time. This dynamic adaptation allows optimal resource utilization for different delay requirements, preventing both resource waste and process fluctuations.
2Adaptability or versatility
If multiple output ports are provided on a single delay chain, then different delay processing can be implemented, but driving capability is insufficient when processing short delays
Solution Approach 1:
The circuit dynamically switches between series and parallel configurations of delay sub-circuits based on the required delay time. For short delays, sub-circuits are connected in parallel to enhance driving capability, while for longer delays, they are connected in series to achieve the required delay duration.
Solution Approach 2:
Multiple delay sub-circuits are merged in parallel configuration when processing short delays, combining their driving capabilities to ensure sufficient signal strength while achieving the required short delay time.
3Loss of time
If delay sub-circuits are connected in series, then longer delay times are achieved, but resource utilization is low for short delay requirements
Solution Approach 1:
The circuit dynamically reconfigures the connection topology of delay sub-circuits based on the required delay time. For short delays, sub-circuits are connected in parallel to maintain high resource utilization, while for longer delays, they are connected in series to achieve the required delay duration.
Solution Approach 2:
The circuit changes the operational parameters by altering the connection configuration (series or parallel) of delay sub-circuits. This parameter change allows the same hardware resources to be efficiently utilized for different delay time requirements, maximizing resource utilization across various operating conditions.
Data Source
AI summary
A delay circuit, a pulse generation circuit, a chip, and a server is disclosed. The delay circuit includes a control unit and at least two delay sub-circuits. Input ends of the delay sub-circuits are connected to each other. Output ends of the delay sub-circuits are connected to each other. The output end of each delay sub-circuit is connected to an input end of an adjacent delay sub-circuit through a switch unit. Each delay sub-circuit includes a delay unit and a switch unit. The delay unit is configured to perform delay processing on an input pulse signal. The switch unit is configured to control the delay sub-circuit to or not to be connected. The control unit is connected to all the switch units, and is configured to separately control a plurality of switch units to be turned on or off, so as to perform corresponding delay processing on the pulse signal.