Reconfigurable Delay Circuit for Transistor Variation Measurement
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Solution Overview
Problem
Conventional delay monitor circuits require a large number of circuits to estimate inter-chip and on-chip variations in transistor characteristics, leading to increased chip area and manufacturing costs.
Innovation Solution
A reconfigurable delay circuit with independently controlled pass transistors allows for various delay characteristics, enabling a single circuit to mimic different configurations, reducing the need for multiple delay monitor circuits and minimizing chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple conventional delay circuits are used to measure different delay characteristics, then measurement precision is improved, but chip area increases
Solution Approach 1:
The delay circuit is designed with reconfigurable pass transistors that can be controlled to create different circuit configurations, enabling a single circuit to perform multiple measurement functions that previously required separate circuits for nMOS and pMOS delay characteristics
Solution Approach 2:
The pass transistors are independently controllable, allowing the circuit configuration to be dynamically changed during operation to switch between different delay measurement modes, transforming a static circuit into a dynamically reconfigurable one
2Measurement precision
If multiple conventional delay circuits are used to estimate inter-chip and on-chip variations, then measurement precision is improved, but device complexity increases
Solution Approach 1:
A single delay circuit incorporates multiple measurement capabilities through reconfigurable pass transistors, eliminating the need for multiple separate circuits and thereby reducing overall device complexity while maintaining measurement precision
Solution Approach 2:
The circuit combines multiple delay measurement functions into one unified structure by merging the functionality of what would have been separate nMOS and pMOS delay circuits into a single reconfigurable unit
Data Source
Figure 1A~1B
Figure 2~3
Figure 4A~4C
AI summary
A delay circuit (10) contains a first inversion circuit including a pull-up circuit (2) and a pull-down circuit (3), and a second inversion circuit including a pull-up circuit (4) and a pull-down circuit (5). The delay circuit further contains a first pass transistor (6) connected in series to the pull-up circuit in the first inversion circuit between a power supply potential and an output node (Out), a second pass transistor (7) connected in series to the pull-down circuit in the first inversion circuit between a ground potential and the output node, a third pass transistor (8) connected in series between the input node (In) and the pull-up circuit in the second inversion circuit, and a fourth pass transistor (9) connected in series between the input node and the pull-down circuit in the second inversion circuit. A delay characteristic of the delay circuit is changed by a combination of control signals (C1 to C4) applied to gates of the first to fourth pass transistors.