Reconfigurable Mixed-Signal Distributed Arithmetic System

Solution Overview

Problem

Existing mixed-signal processing technologies face challenges in optimizing power consumption and area usage while efficiently performing distributed arithmetic functions, particularly in portable electronics where analog signal processing is preferred over digital-to-analog conversion.

Innovation Solution

A reconfigurable mixed-signal distributed arithmetic system utilizing tunable voltage references and digital circuit elements to perform distributed arithmetic functions, incorporating floating-gate transistors for analog storage and programmability, which reduces power consumption and area usage by replacing multipliers and adders with a single gain multiplication and coefficient array.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a large memory is used for lookup table in distributed arithmetic, then computational efficiency is improved, but power consumption and area usage increase

Engineering Contradiction:

Improvecomputational efficiencyVSAvoidpower consumption

Core Design Contradiction:

ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent segments the distributed arithmetic computation into two parts: a compressed lookup table stored in memory, and a post-processing circuit that performs the actual computation. The LUT is compressed to store only essential data, while the segmented computation is completed using simple digital logic circuits, thereby reducing memory size and power consumption while maintaining computational efficiency.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent merges the advantages of both memory-based lookup and simple digital logic by combining a compressed LUT with a post-processing circuit. This hybrid approach allows the system to benefit from the speed of memory lookup while using low-power digital logic for the remaining computation, thus resolving the power-efficiency tradeoff.

Inventive Principle:

Principle #5Merging (Combining)

2Productivity

If a large memory is used for lookup table in distributed arithmetic, then computational efficiency is improved, but area usage increases

Engineering Contradiction:

Improvecomputational efficiencyVSAvoidarea usage

Core Design Contradiction:

ProductivityVSArea of stationary object

Solution Approach 1:

The patent segments the distributed arithmetic computation into two parts: a compressed lookup table stored in memory, and a post-processing circuit that performs the actual computation. The LUT is compressed to store only essential data, while the segmented computation is completed using simple digital logic circuits, thereby reducing memory size and power consumption while maintaining computational efficiency.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent merges the advantages of both memory-based lookup and simple digital logic by combining a compressed LUT with a post-processing circuit. This hybrid approach allows the system to benefit from the speed of memory lookup while using low-power digital logic for the remaining computation, thus resolving the power-efficiency tradeoff.

Inventive Principle:

Principle #5Merging (Combining)

3Adaptability or versatility

If digital signal processing is used for analog input processing, then functionality is improved, but power consumption increases due to analog-to-digital conversion

Engineering Contradiction:

ImprovefunctionalityVSAvoidpower consumption

Core Design Contradiction:

Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

The patent extracts the essential computational function from the full digital signal processing chain by implementing a hybrid analog-digital system. The analog input is processed through a compressed LUT in analog domain, and only the essential post-processing is done digitally, thereby maintaining functionality while eliminating unnecessary analog-to-digital conversion and reducing power consumption.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent creates a multi-functional system that can process analog inputs directly through the compressed LUT approach, eliminating the need for separate ADC and full digital processing chains. This universal approach works for various signal processing applications while maintaining low power consumption.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables compact, low-power implementations of high-order FIR filters and DFT functions, improving computational efficiency and reducing errors, while maintaining accuracy and flexibility for adaptive systems.

Implementation Method 1

incorporating floating-gate transistors for analog storage and programmability

Methodology Applied

Scientific EffectFloating-gate transistor storage: Capacitance

Data Source

PatentUS7348909B2Reconfigurable mixed-signal VLSI implementation of distributed arithmetic

Publication Date: 2008.03.25 GEORGIA TECH RES CORP

AI summary

Disclosed herein is a reconfigurable mixed signal distributed arithmetic system including: an array of tunable voltage references operable for receiving a delayed digital input signal; a combination device in electrical communication with the array of tunable floating-gate voltage references that selectively combines an output of the array of tunable voltage references into an analog output signal; and a feedback element in electrical communication with the combination device, wherein the array of tunable voltages and the delayed digital input signal combine to perform a distributed arithmetic function and the reconfigurable mixed signal distributed arithmetic system responsively generates the analog output signal.