Reconfigurable DSP Vector Engine for Mixed Signal Processing
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Solution Overview
Problem
Current digital signal processing systems struggle to efficiently handle the diverse compute requirements of high-speed digital signal processing and machine learning/artificial intelligence algorithms, which often necessitate separate compute engines and result in increased power consumption and hardware footprint.
Innovation Solution
A flexible hardware architecture, such as an integrated accumulator, is proposed that combines digital signal processing and neural network processing capabilities within a single platform, allowing for configurable processing elements to perform a wide range of matrix operations and support both complex and real number arithmetic, thereby accelerating wireless signal processing and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If separate compute engines are used for digital signal processing and machine learning algorithms, then processing capability for each specific function is improved, but hardware footprint and power consumption increase
Solution Approach 1:
The patent combines digital signal processing capabilities and neural network processing capabilities into a single integrated compute engine. The processing element includes both a complex number MAC unit for DSP operations and a real number MAC unit for neural network operations, allowing both function types to share the same hardware resource rather than requiring separate dedicated engines for each.
Solution Approach 2:
The processing element is designed as a universal compute unit that can perform multiple functions through configuration. By using multiplexers to route inputs and control signals, the same physical hardware can be dynamically configured to execute either complex number DSP operations or real number neural network operations, making the hardware adaptable to different computational workloads.
2Productivity
If separate compute engines are used for digital signal processing and machine learning algorithms, then processing capability for each specific function is improved, but power consumption increases
Solution Approach 1:
The patent combines digital signal processing capabilities and neural network processing capabilities into a single integrated compute engine. The processing element includes both a complex number MAC unit for DSP operations and a real number MAC unit for neural network operations, allowing both function types to share the same hardware resource rather than requiring separate dedicated engines for each.
Solution Approach 2:
The processing element is designed as a universal compute unit that can perform multiple functions through configuration. By using multiplexers to route inputs and control signals, the same physical hardware can be dynamically configured to execute either complex number DSP operations or real number neural network operations, making the hardware adaptable to different computational workloads.
3Device complexity
If fixed data width interfaces are used in programmable logic devices, then interface simplicity is maintained, but ability to accommodate various data transmission widths is reduced
Solution Approach 1:
The interface is designed with dynamic reconfigurability, allowing the data width to be adjusted based on the specific computational task. Multiplexers are used to selectively route data bits of varying widths to the appropriate processing units, enabling the interface to adapt between narrow and wide data transmissions without requiring multiple fixed-width interface circuits.
Solution Approach 2:
The interface parameters, specifically the data width, are made changeable through control signals that configure the multiplexers and routing logic. This allows the same physical interface to operate at different data widths (e.g., 8-bit, 16-bit, 32-bit) depending on the requirements of the programmed function, maintaining simplicity while achieving versatility.
Data Source
AI summary
Systems and methods described herein may relate to providing a dynamically configurable circuitry able to process data associated with a variety of matrix dimensions using one or more complex number operations, one or more real number operations, or both. Configurations may be applied to the configurable circuitry to program the configurable circuitry for a next operation. The configurable circuitry may process data according to a variety of operations based at least in part on operation of a repeated processing element coupled in a compute network of processing elements.