Reconfigurable Dynamic Cache System for Multi-Core Latency

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Solution Overview

Problem

Current cache architectures are inadequate in managing the increasing latency between processor speed and memory access time, limiting the performance of memory-intensive applications, especially in multi-processor systems where efficient cache operation and wide memory bandwidth are critical.

Innovation Solution

A reconfigurable dynamic cache system that varies its operation strategy based on demand from external general processor cores, utilizing a virtualized hybrid core system, which includes a memory processing element with a cache memory, front end, and memory processing core to select and dynamically update operational modes for optimal data request processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If conventional cache architectures are used, then the system structure is simple, but the latency between processor speed and memory access time increases

Engineering Contradiction:
Improvelatency between processor speed and memory access timeVSAvoidcache architecture complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The cache controller dynamically selects between different operational modes (write-through, write-back, write-allocate, write-no-allocate) based on real-time analysis of write request patterns, transforming the static cache architecture into a dynamic system that adapts to varying workload characteristics to minimize latency

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes operational parameters (cache write policy, cache replace policy) based on detected workload patterns, allowing the cache to optimize its behavior for different access patterns and thereby reduce memory access latency without requiring a completely different architecture

Inventive Principle:
Principle #35Parameter changes

2Adaptability or versatility

If static cache operation strategy is used, then the device complexity is low, but the adaptability to different application demands decreases

Engineering Contradiction:
Improveadaptability to different application demandsVSAvoidcache operation strategy complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The cache controller implements feedback mechanisms by monitoring write request patterns and using this information to dynamically adjust operational modes, enabling the system to adapt to different application demands while maintaining manageable complexity through automated control

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The cache system performs self-optimization by automatically analyzing its own operational patterns and selecting appropriate modes without external intervention, improving adaptability while keeping the control mechanism relatively simple and self-contained

Inventive Principle:
Principle #25Self-service

3Productivity

If dynamic mode selection is implemented, then the cache efficiency is improved, but the front end activity complexity increases

Engineering Contradiction:
Improvecache efficiencyVSAvoidfront end activity complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The system monitors only the necessary front end activities (write request patterns) required for mode selection rather than comprehensively tracking all cache operations, improving cache efficiency while limiting the complexity increase to only the essential monitoring functions

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS9348756B2Active memory processor system
Publication Date: 2016.05.24 SDEP CORP
  • US9348756B2 patent drawing
  • US9348756B2 patent drawing
  • US9348756B2 patent drawing

AI summary

In general, the present invention relates to data cache processing. Specifically, the present invention relates to a system that provides reconfigurable dynamic cache which varies the operation strategy of cache memory based on the demand from the applications originating from different external general processor cores, along with functions of a virtualized hybrid core system. The system includes receiving a data request, selecting an operational mode based on the data request and a predefined selection algorithm, and processing the data request based on the selected operational mode.