Reconfigurable Microprocessor Execution Path for Dynamic Instruction Handling
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Solution Overview
Problem
Conventional microprocessors and classical architectures are inadequate for evolving application requirements due to fixed instruction sets and limitations in clock speeds, making it challenging to optimize execution speed and adapt to diverse application needs.
Innovation Solution
A microprocessor architecture with a trusted instruction set execution path and a reconfigurable execution path, allowing dynamic reconfiguration based on criteria such as power consumption, processing power, and application requirements, using field-programmable gate arrays and content addressable memory to handle instructions efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a fixed instruction set is used in conventional microprocessors, then the architecture is simple and reliable, but it cannot adapt to evolving application requirements and achieves optimal execution speed
Solution Approach 1:
The patent implements a dynamically reconfigurable execution path that can be activated or deactivated based on runtime conditions. The execution path includes reconfigurable logic blocks that can be programmed to handle different instruction types, allowing the processor to adapt its functionality dynamically while maintaining a relatively simple base architecture.
Solution Approach 2:
The processor architecture is segmented into a fixed instruction set execution path and a reconfigurable execution path. This segmentation allows the system to maintain the simplicity and reliability of the fixed path while adding adaptability through the modular reconfigurable path, resolving the contradiction between simplicity and adaptability.
2Productivity
If clock speed is increased to improve execution speed, then processing performance improves, but power consumption increases and physical limits are reached
Solution Approach 1:
Instead of relying solely on increasing clock speed, the patent introduces a dynamically reconfigurable execution path that can be activated based on computational needs. This allows the processor to optimize execution speed for specific tasks without continuously operating at maximum clock speed, thereby reducing overall power consumption while maintaining high productivity when needed.
3Productivity
If a reconfigurable execution path is added to handle extended instructions, then adaptability and execution speed improve, but device complexity and security risks increase
Solution Approach 1:
The processor is divided into distinct execution paths: a fixed instruction set path and a reconfigurable execution path. This segmentation isolates the complexity of the reconfigurable path, allowing it to be managed separately while the fixed path maintains its simplicity and reliability. The system can select which path to use based on the instruction type, managing complexity effectively.
Solution Approach 2:
An intermediary control mechanism manages the reconfigurable execution path, handling the complexity of configuration and security verification. This intermediary layer shields the core processing logic from the complexity of reconfiguration management, allowing execution speed improvements without proportionally increasing overall architectural complexity.
4Productivity
If the reconfigurable execution path is activated to handle specific instructions, then processing efficiency improves, but security verification overhead increases
Solution Approach 1:
Security verification for the reconfigurable execution path is performed in advance, before runtime activation. Configuration data is verified and authenticated prior to being loaded into the reconfigurable logic, so that when the execution path needs to be activated, the verification overhead is minimal. This preliminary action resolves the contradiction by shifting security checks to a less critical time window.
Data Source
AI summary
Described is microprocessor architecture that includes at least one reconfigurable execution path (e.g., implemented via FPGAs or CPLDs). When an instruction is fetched, a mechanism determines whether the reconfigurable execution path (and/or which path) will handle that instruction. A content addressable memory may be used to determine the execution path when fed the instruction's operational code, or an arbiter and multiplexer may resolve conflicts if multiple instruction decode blocks recognize the same instruction. The execution path may be dynamically reconfigured, activated or deactivated as needed, such as to extend an instruction set, to optimize instructions for a particular application program, to implement a peripheral device, to provide parallel computing, and/or based on power consumption and/or processing power needs. Security may be provided by having the reconfigurable execution path loaded from an extension file that is associated with metadata, including security information.