Reconfigurable Execution Slices for Parallel Instruction Processing
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Solution Overview
Problem
Conventional processor cores are limited by fixed instruction execution architectures, leading to underutilization of resources when executing non-vector instructions, as they are not optimized for instructions of varying widths, resulting in inefficient use of processor resources.
Innovation Solution
A processor core with reconfigurable execution slices, including a master and slave execution slice, and control logic that detects wider instructions to reserve issue cycles for parallel execution across both slices, allowing for efficient handling of instructions of varying widths by combining resources when necessary.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a fixed instruction execution architecture is used, then the control logic is simple and stable, but the processor resources are not fully utilized when executing non-vector instructions
Solution Approach 1:
The execution slices are designed to be reconfigurable, allowing the processor to dynamically adjust the number of active slices and their configuration based on the instruction width being executed. This enables the system to adapt between executing narrow scalar instructions using fewer slices and wide vector instructions using all slices, thereby improving resource utilization without requiring a completely complex control structure
Solution Approach 2:
Each execution slice is designed with multi-functionality to handle different instruction widths (32-bit, 64-bit, 128-bit). The slices can operate independently for scalar instructions or be combined in parallel for vector instructions, allowing the same hardware structure to serve multiple purposes and improve overall processor efficiency
2Productivity
If execution slices are configured for fixed width instructions, then the architecture is simple, but resources are underutilized when executing instructions of varying widths
Solution Approach 1:
The system dynamically configures the number of active execution slices based on the instruction width detected by the control logic. When a wide instruction is detected, additional slices are activated and synchronized to execute the instruction in parallel, providing both adaptability to different instruction widths and efficient resource utilization
Solution Approach 2:
Multiple execution slices can be merged to execute wider instructions. When a 128-bit instruction is detected, two 64-bit slices work in parallel to execute the instruction, effectively combining their resources to handle the wider data width while maintaining efficient resource utilization
3Productivity
If parallel execution across multiple slices is implemented, then throughput is improved, but coordination complexity increases
Solution Approach 1:
The control logic acts as an intermediary that manages the coordination between multiple execution slices. It detects instruction widths, determines the appropriate number of slices to activate, and synchronizes their operation, thereby enabling parallel execution to improve throughput while the control logic handles the coordination complexity
Data Source
AI summary
An execution slice circuit for a processor core has multiple parallel instruction execution slices and provides flexible and efficient use of internal resources. The execution slice circuit includes a master execution slice for receiving instructions of a first instruction stream and a slave execution slice for receiving instructions of a second instruction stream and instructions of the first instruction stream that require an execution width greater than a width of the slices. The execution slice circuit also includes a control logic that detects when a first instruction of the first instruction stream has the greater width and controls the slave execution slice to reserve a first issue cycle for issuing the first instruction in parallel across the master execution slice and the slave execution slice.