Reconfigurable FEC Encoder for Single-Cycle Standard Switching
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Solution Overview
Problem
Conventional implementations of convolutional and turbo encoders require significant configuration data and multiple clock cycles to switch between different communications standards, limiting their efficiency in handling multiple standards and input bits per clock cycle.
Innovation Solution
A reconfigurable apparatus with a first circuit to receive configuration signals and generate matrix elements for encoding input signals according to specific communications standards, allowing for hardware-only reconfiguration and handling multiple input bits per clock cycle, with the ability to switch between standards in a single clock cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conventional encoder simultaneously supports many different standards, then the encoder can handle multiple communications standards, but the configuration data required increases significantly and many clock cycles are used to configure the encoder
Solution Approach 1:
The configuration data is segmented into multiple groups, where each group corresponds to a specific communications standard. The encoder receives a configuration signal that identifies the current standard and selectively activates only the relevant segment of configuration data, rather than loading all configuration data at once. This segmentation allows the encoder to switch between standards by activating different segments, reducing the time required for reconfiguration.
Solution Approach 2:
The configuration data for multiple standards is prepared in advance and stored in the encoder's internal registers in a segmented manner. When the encoder is initialized, all configuration data is pre-loaded into the registers, but only the relevant segment is activated based on the configuration signal. This preliminary preparation eliminates the need for external configuration loading during standard switching, enabling single-clock-cycle reconfiguration.
2Productivity
If a conventional encoder handles a single input bit per clock cycle, then the encoding process is simple, but the throughput is limited
Solution Approach 1:
Multiple encoding operations are merged into a single clock cycle by processing multiple input bits simultaneously. The encoder uses parallel processing paths and combined logic circuits that can handle several input bits in one cycle, thereby increasing throughput. The configuration signal controls which parallel paths are activated based on the current communications standard, allowing the encoder to adapt its parallelism level to match the required standard while maintaining high throughput.
Data Source
AI summary
An apparatus generally including a first circuit and a second circuit. The first circuit may be configured to (i) receive a configuration signal that identifies a current one of a plurality of communications standards and (ii) generate a plurality of matrix elements based on the configuration signal. The second circuit may include a plurality of matrixes. The second circuit may be configured to (i) fill the matrixes with the matrix elements and (ii) generate an encoded signal by forward error correction encoding an input signal using the matrixes. The encoded signal generally complies with the current communications standard.