Reconfigurable Mixed-Radix FFT Processor Pipeline Architecture
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Solution Overview
Problem
Existing FFT processor architectures face challenges in reducing computing time and hardware cost due to high computational complexity and inefficient utilization of butterfly units and multiplexers, particularly in reconfiguring for various FFT sizes.
Innovation Solution
A pipeline-based reconfigurable mixed-radix FFT processor is designed, decomposing N-point FFT into at most four computation stages using a first general butterfly, a second general butterfly, and a reconfigurable butterfly, with a reconfigurable architecture that reuses the first general butterfly and minimizes storage elements and multiplexers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a traditional pipeline-based FFT architecture is used, then the throughput rate is high, but the hardware complexity and computing time increase due to excessive butterfly units and multiplexers
Solution Approach 1:
The N-point FFT is decomposed into multiple stages with each stage handling a specific radix operation (radix-2, radix-4, or radix-8). This segmentation allows the complex FFT computation to be broken down into manageable stages, reducing the overall hardware complexity while maintaining high throughput through pipelined execution of these segmented stages.
Solution Approach 2:
The architecture employs reconfigurable butterfly units that can dynamically change their operation mode between different radices (2, 4, or 8) based on the specific FFT size required. This dynamic reconfiguration eliminates the need for dedicated hardware for each radix type, reducing hardware complexity while preserving productivity through flexible adaptation to different computation requirements.
2Loss of time
If more butterfly units are used to reduce computing time, then the computation speed increases, but the hardware cost and area increase
Solution Approach 1:
The butterfly units are designed with multi-functionality, capable of performing radix-2, radix-4, and radix-8 operations within the same hardware structure. This universality allows a single set of butterfly units to handle different FFT sizes and stages, reducing the total number of hardware elements needed while maintaining fast computation through efficient utilization of these versatile units across multiple operation modes.
3Productivity
If the architecture is fixed for a specific FFT size, then the optimization for that size is maximized, but the adaptability to other FFT sizes is reduced
Solution Approach 1:
The architecture incorporates reconfigurable elements that allow dynamic adaptation to different FFT sizes (16-point to 4096-point). The butterfly units can be configured to operate in different radix modes, and the interconnection structure can be reconfigured to support various stage combinations, enabling the same hardware to achieve optimized performance across multiple FFT size requirements rather than being fixed to a single configuration.
Solution Approach 2:
The system changes operational parameters (radix value, number of stages, data flow configuration) to adapt to different FFT sizes. By modifying these parameters rather than changing the physical hardware structure, the architecture maintains high computation efficiency across various FFT lengths while preserving adaptability to different application requirements.
4Quantity of substance
If storage elements are increased to support larger FFT sizes, then the capacity increases, but the hardware cost and complexity increase
Solution Approach 1:
Storage elements are organized into stage-specific buffers that are allocated according to the actual computation requirements of each FFT stage. This segmentation allows the storage system to provide adequate capacity for larger FFT sizes when needed, while using minimal storage resources for smaller FFT operations, thereby reducing overall hardware complexity while maintaining the capacity to handle various FFT lengths.
Data Source
AI summary
The present invention discloses a fast Fourier transform (FFT) processor based on multiple-path delay commutator architecture. A pipelined architecture is used and is divided into 4 stages with 8 parallel data path. Yet, only three physical computation stages are implemented. The process or uses the block floating point method to maintain the signal-to-noise ratio. Internal storage elements are required in the method to hold and switch intermediate data. With good circuit partition, the storage elements can adjust their capacity for different modes, from 16-point to 4096-point FFTs, by turning on or turning off the storage elements.