Reconfigurable Orthogonal Transform Architecture for Variable FFT Sizes
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Solution Overview
Problem
Existing hardware implementations of orthogonal transforms, such as FFT/IFFT, face challenges in flexibility and energy efficiency due to their fixed architecture, which complicates the support of varying vector sizes and increases silicon area and power consumption.
Innovation Solution
A reconfigurable architecture that adapts to the size of the FFT vectors by modifying interconnection structures, memory, and using Radix2, Radix22, Radix4, or Radix8 formats, allowing for on-line determination of transform sizes and efficient processing through simplified interconnection and multiplexing, eliminating unnecessary hardware blocks and optimizing clock cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a fixed architecture is used for orthogonal transforms, then the hardware implementation is simple, but it cannot support varying vector sizes and requires large silicon area for maximum flexibility
Solution Approach 1:
The patent implements a reconfigurable architecture where the interconnection structure can be dynamically adjusted based on the input vector size. The butterfly units and interconnection network are designed to be reconfigurable, allowing the same hardware to adapt to different FFT sizes (e.g., 16-point, 32-point, 64-point) by changing the interconnection pattern and enabling/disabling specific processing stages, thereby eliminating the need for multiple fixed architectures for different sizes.
Solution Approach 2:
The patent designs a universal FFT processor that can handle multiple transform sizes and types (FFT, IFFT, DCT, DST) using the same core hardware resources. The butterfly units are designed with multi-functionality to perform different operations depending on configuration, and the interconnection network can be reconfigured to support various algorithm structures, making a single device capable of replacing multiple dedicated processors.
2Adaptability or versatility
If a fixed architecture is used for orthogonal transforms, then the hardware structure is stable, but power consumption increases due to unnecessary hardware blocks
Solution Approach 1:
The reconfigurable architecture allows the system to dynamically enable only the necessary processing stages and interconnection paths required for the current transform size. For example, when performing a 16-point FFT, only the first four stages of butterfly units are activated, while later stages remain disabled. This dynamic configuration reduces the number of active hardware blocks and their associated power consumption compared to a fixed architecture that must support the maximum size.
Solution Approach 2:
The patent implements mechanisms to discard (disable) unnecessary hardware blocks during operation based on the current processing requirements. Control logic selectively enables or disables specific butterfly units, interconnection paths, and memory blocks depending on the transform size and type being performed, thereby reducing power consumption by keeping only the essential components active while recovering the ability to use full resources when needed.
3Adaptability or versatility
If a reconfigurable architecture is used, then flexibility for varying vector sizes is improved, but device complexity increases
Solution Approach 1:
The patent divides the FFT processing into distinct stages, each handling a specific level of the transform decomposition. The interconnection network is segmented into multiple configurable layers, and the butterfly units are organized in modular groups. This segmentation allows independent configuration of each stage, simplifying the control logic for reconfiguration while maintaining flexibility. Each segment can be independently enabled or configured based on the required transform size.
Solution Approach 2:
The reconfigurable architecture implements a standardized maximum-capability structure that includes all possible processing stages needed for the largest supported transform size. For smaller transforms, the system uses only the necessary subset of stages, leaving the remaining stages in a default disabled state. This approach simplifies the hardware design by providing a uniform template that works for all sizes, avoiding the need for complex conditional structuring, while the control logic selectively activates only the required portion.
Data Source
AI summary
A reconfigurable architecture for and method of performing a fast orthogonal transform of vectors in multiple stages, the size of a vector being N, wherein N can vary and the number of stages is a function of N, the architecture comprising:a computational unit configured and arranged so as to include one or more butterfly units; a block including one or more multipliers coupled to the output of the computational unit, configured and arranged so as to perform all of the butterfly computations for at least one stage of the transform; a storage unit configured and arranged so as to store the intermediate results of the butterfly computations and predetermined coefficients for use by the computational unit for performing each butterfly computation, the storage unit including memory and multiplexing architecture; the storage unit including memory and multiplexing architecture; a multiplexer unit configured and arranged so as to time multiplex all of the butterfly computations of the transform using said computation unit for the one stage so that only one computation unit is required for the stage; and a controller configured and arranged so as to provide coefficients to the computational unit, and control the sizes of memory and multiplexing architecture in the storage unit; wherein the multipliers' coefficients, the coefficients of the computational unit, the sizes of memories, and multiplexing architecture, for each stage are modified as a function of the value of N.The architecture can be implemented as an integrated chip, and used in communication devices.