Reconfigurable FHE Compute Circuitry for Mixed Polynomial Degrees
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Solution Overview
Problem
Existing compute circuitry optimized for specific polynomial degrees, such as 16K, suffer from severe underutilization and performance degradation when smaller polynomials like 1K are mapped onto them, leading to inefficient use of resources and increased latency in FHE operations.
Innovation Solution
A reconfigurable FHE accelerator that allows mapping multiple independent 1024-degree polynomials onto a larger 16K polynomial, utilizing compute elements in a bypass mode and employing data movement instructions to convert coefficients from shuffled to contiguous form, optimizing resource utilization and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If compute circuitry is optimized for specific polynomial degrees (e.g., 16K), then performance for that specific degree is maximized, but resource utilization deteriorates when smaller polynomials (e.g., 1K) are mapped onto it
Solution Approach 1:
The compute circuitry incorporates reconfigurable compute elements that can dynamically switch between different operational modes (bypass mode and compute mode) based on the polynomial degree being processed. This dynamic reconfiguration allows the same hardware to efficiently handle both small (1K) and large (16K) polynomials without fixed performance characteristics, resolving the contradiction between optimized performance for specific degrees and adaptability across degrees.
Solution Approach 2:
The patent implements a universal compute circuitry design where compute elements can serve multiple functions: acting as bypass paths for small polynomials or as full compute units for large polynomials. This multi-functionality allows a single hardware architecture to universally handle FHE operations across different polynomial degrees, eliminating the need for separate optimized circuits for each degree and thereby improving both performance and resource utilization adaptability.
2Quantity of substance
If compute circuitry is designed for large polynomials (16K), then capacity is maximized, but efficiency deteriorates when processing smaller polynomials (1K)
Solution Approach 1:
The compute circuitry is segmented into multiple independent compute elements that can be selectively activated based on the polynomial size. For small polynomials (1K), only a subset of compute elements are active, while for large polynomials (16K), all compute elements are activated. This segmentation allows the system to maintain high capacity for large polynomials while improving efficiency for small polynomials by avoiding activation of unnecessary compute elements, thus resolving the contradiction between capacity and efficiency.
Solution Approach 2:
The patent employs parameter changes in the form of reconfigurable compute elements that can switch between bypass mode and compute mode based on the polynomial degree parameter. When processing small polynomials, the compute elements change their operational parameter to bypass mode, reducing computational overhead and improving efficiency. When processing large polynomials, they switch to compute mode to maximize capacity utilization, thereby resolving the contradiction between capacity and efficiency across different polynomial sizes.
3Productivity
If fixed polynomial size mapping is used, then hardware utilization is maximized for that size, but latency increases when polynomial size changes
Solution Approach 1:
The compute circuitry implements dynamic reconfiguration capabilities that allow compute elements to switch between bypass mode and compute mode in response to changing polynomial sizes. This dynamic adaptation eliminates the need for fixed mapping configurations, enabling the system to maintain high hardware utilization across different polynomial sizes while reducing processing latency by avoiding reconfiguration delays associated with fixed-size mappings.
Data Source
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AI summary
A reconfigurable compute circuitry to perform Fully Homomorphic Encryption (FHE) enables a full utilization of compute resources and data movement resources by mapping multiple N * 1024 polynomials on to a (M*N)* 1024 polynomial. To counteract the shuffling of the coefficients during Number-Theoretic-Transforms (NTT) and inverse-NTT operations, compute elements in the compute circuitry operate in a bypass mode that is enabled by a data movement instruction, to convert from the shuffled form to contiguous form without modifying the values of the coefficients.