Reconfigurable Digital Filter for Multi-Rate Receiver Signals
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Solution Overview
Problem
Existing digital bandpass filter systems require large and expensive Application-Specific Integrated Circuits (ASICs) or multiple Field-Programmable Gate Arrays (FPGAs to process digital signals at different rates, which is problematic in space-constrained applications like single-module radar receivers due to their size and lack of configurability.
Innovation Solution
A configurable digital filter that can process signals at different rates using shared filtering and adjustable filter lengths, implemented in a single FPGA, with user-definable coefficients and a controller for mode selection and coefficient management, allowing it to handle both narrowband and wideband signals efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If plural digital filters are employed to process signals at different rates, then signal processing capability is improved, but device size and cost increase
Solution Approach 1:
The patent implements a single reconfigurable digital filter that can process signals at multiple different rates by dynamically adjusting its filter coefficients and structure. This universal filter replaces multiple dedicated filters, enabling the system to handle both narrowband and wideband signals with a single device, thereby reducing circuit board space while maintaining signal processing capability
Solution Approach 2:
The filter employs dynamic reconfiguration capabilities where filter coefficients, lengths, and structures can be adjusted in real-time based on the input signal characteristics. This allows the same hardware to adapt to different signal processing requirements (different rates and bandwidths) without requiring separate fixed filters for each case
2Adaptability or versatility
If multiple FPGAs are used to implement processing paths, then processing flexibility is improved, but device complexity and cost increase
Solution Approach 1:
The patent consolidates multiple processing paths into a single FPGA by implementing a reconfigurable filter that can be programmed to perform different filtering operations. This single-device solution provides the same processing flexibility as multiple FPGAs would offer, but with reduced device complexity and lower cost
3Ease of manufacture
If fixed filter designs are used, then manufacturing simplicity is improved, but adaptability to different signal rates deteriorates
Solution Approach 1:
The filter design incorporates dynamic coefficient loading and reconfiguration capabilities that allow the same manufactured hardware to adapt to different signal rates and processing requirements. The filter can be programmed with different coefficients and structures as needed, combining manufacturing simplicity with operational adaptability
Data Source
AI summary
An efficient configurable signal filter. The filter includes a first mechanism for receiving a first signal of a first type and a second signal of a second type. A second mechanism selectively filters the first signal during a first mode of operation, and filters the second signal during a second mode of operation. A third mechanism generates control signals. A fourth mechanism automatically configures the second mechanism to operate in the first mode of operation or the second mode of operation based on the control signals. In a specific embodiment, the first type of signal is characterized by a first rate, and the second type of signal is characterized by a second rate. The first signal and the second signal are digital ADC outputs. The second mechanism includes plural filter blocks, each having one or more Multiply-Accumulate (MAC) pipes. Each of the one or more MAC pipes include one or more MAC blocks that are each associated with a coefficient memory data structure of a coefficient memory. The third mechanism or a user selects coefficients from each memory data structure to apply to each MAC block, thereby selectively affecting filter response. The control signals direct multiplexers or switches to configure the MAC pipes in a serial configuration or a parallel configuration corresponding to the first mode of operation or the second mode of operation, respectively.