Reconfigurable FIR Matrix for Scalable ASIC Filter Throughput
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Solution Overview
Problem
Current digital signal processing (DSP) applications face challenges with Finite Impulse Response (FIR) filters, particularly in terms of flexibility, cost-effectiveness, and efficiency when implemented in Application Specific Integrated Circuits (ASICs) or Field Programmable Gate Arrays (FPGAs), as they require significant resources and incur high non-recurring engineering (NRE) costs and suffer from size, weight, and power inefficiencies.
Innovation Solution
A Scalable Finite Impulse Response (SFIR) filter design that includes a pre-processing section, a post-processing section, and a finite impulse response filtering matrix with re-configurable data throughput between filter taps, allowing for flexible configuration and efficient resource utilization on an ASIC, similar to FPGAs without the inefficiencies of SWAP costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If ASIC is used for FIR filter implementation, then efficiency is improved, but flexibility deteriorates
Solution Approach 1:
The patent implements reconfigurable signal paths that allow the filter structure to dynamically change its configuration. The signal paths can be reconfigured to support different filter lengths and types (e.g., Hilbert transforms, decimators, interpolators) while maintaining the ASIC's efficient hardware architecture, thus resolving the contradiction between fixed efficiency and flexible adaptability.
Solution Approach 2:
The FIR filter is designed with a universal architecture that can perform multiple filtering functions through reconfiguration of signal paths. The same hardware structure supports various filter types and lengths, making the ASIC efficient for multiple applications rather than being dedicated to a single function.
2Adaptability or versatility
If FPGA is used for FIR filter implementation, then flexibility is improved, but size, weight, and power deteriorate
Solution Approach 1:
The filter is segmented into discrete filter taps with independent signal paths. This segmentation allows the ASIC to implement only the necessary filtering resources for a given application, reducing overall power consumption while maintaining flexibility through selective activation of different signal paths.
Solution Approach 2:
The patent employs reconfigurable parameters including filter length, data throughput, and signal path activation. By dynamically changing these parameters, the ASIC can optimize power consumption for different operating conditions while maintaining FPGA-like flexibility, avoiding the high SWAP costs of FPGAs.
3Adaptability or versatility
If filter size increases, then filtering capability is improved, but manufacturing difficulty increases
Solution Approach 1:
The signal paths are designed to be reconfigurable, allowing the same physical hardware to support different filter sizes and configurations. This dynamic reconfiguration capability enables large filtering capability without proportionally increasing manufacturing complexity, as the same routed paths can serve multiple filter size requirements.
Data Source
AI summary
A Scalable Finite Impulse Response (“SFIR”) filter is disclosed. The SFIR filter includes a pre-processing section, a post-processing section, and a finite impulse response (“FIR”) Matrix. The FIR Matrix includes a plurality of filter taps and a plurality of signal paths in signal communication with each filter tap. The plurality of signal paths are arranged to allow re-configurable data throughput between the each filter tap and the pre-processing section and post-processing section are in signal communication with the FIR Matrix.