Reconfigurable Galois Field FEC Decoder for Optical Inter-Satellite Links

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Solution Overview

Problem

Existing satellite communication systems face challenges in achieving interoperability and high throughput due to the use of different FEC schemes, with ASICs optimized for single code structures and limited correction performance.

Innovation Solution

A reconfigurable decoder architecture that supports multiple FEC schemes, including Open Forward Error Correction and Staircase Codes, using an input loader, decoders, and an interleaver to manage virtual and real bits efficiently, allowing flexible switching between different error correction modes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If ASICs are optimized for single code structure, then device complexity is reduced, but adaptability to different FEC schemes deteriorates

Engineering Contradiction:

Improvesupport for multiple FEC schemesVSAvoiddecoder architecture complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The decoder architecture is designed to support multiple FEC schemes (Open FEC, Staircase Code, and other Galois Field codes) through a unified structure. The interleaver module can be reconfigured to handle different code types, and the decoder core implements generic Galois Field operations that work across multiple code structures, eliminating the need for separate dedicated decoders for each scheme.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The decoder incorporates reconfigurable elements including a dynamically adjustable interleaver that can switch between different interleaving patterns based on the detected code type. The control logic enables the decoder to adapt its operation mode according to the input code structure, allowing a single static hardware architecture to perform multiple dynamic functions.

Inventive Principle:

Principle #15Dynamics

2Productivity

If hard decision decoding is used to achieve high throughput, then productivity is improved, but error correcting capability deteriorates

Engineering Contradiction:

Improvedecoding throughputVSAvoiderror correcting capability

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The decoding process is segmented into multiple independent stages: channel decoding, interleaving, and error correction. The system uses inner-outer concatenated codes where the inner code handles burst errors through interleaving while the outer code provides systematic error correction. This segmentation allows each stage to optimize for its specific function, maintaining high throughput while improving overall error correction performance.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The interleaver acts as an intermediary between the channel decoder and the error correction decoder. It rearranges the decoded bits to distribute burst errors across multiple codewords, converting them into scattered bit errors that are easier to correct. This intermediary structure enables the system to achieve both high throughput from hard decision decoding and improved error correction capability.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Adaptability or versatility

If existing satellite groups use different FEC schemes, then interoperability is improved, but device complexity increases

Engineering Contradiction:

Improveinteroperability between satellite groupsVSAvoidcode structure variety

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The decoder uses reconfigurable parameters including variable interleaver patterns, adjustable code rate ratios, and flexible Galois Field sizes that can be changed based on the detected FEC scheme. The control logic automatically adjusts these parameters when switching between different satellite group standards, enabling interoperability without requiring complex custom hardware for each standard.

Inventive Principle:

Principle #35Parameter changes

4Adaptability or versatility

If virtual and real bits are managed separately in the intermediary buffer, then adaptability to different code methods is improved, but device complexity increases

Engineering Contradiction:

Improvecode method configurabilityVSAvoidbuffer management complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The intermediary buffer is designed as a unified structure that simultaneously stores both virtual bits (for Open FEC) and real bits (for Staircase Code) using the same physical memory resources. The bit mapping logic merges the management of these different bit types into a single control mechanism, reducing the overall complexity compared to having separate buffer management systems for each code method.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS20250337526A1Reconfigurable Galois Field Forward Error Correction Decoder For Optical Inter-Satellite Communication

Publication Date: 2025.10.30 THE RGT UNIV OF MICHIGAN

AI summary

A high-throughput forward error correction (FEC) decoder capable of decoding BCH, RS, Staircase and oFEC codes presented. With a flexible/reconfigurable BCH/RS inner code, it enables adaptive and reliable intersatellite optical communication. The decoder features unprecedented configurability in terms of Galois field (GF) size, code rate, iteration number, and parallel factor, providing a tradeoff between error correction performance, energy, and throughput. Implemented in 12 nm CMOS, the decoder in oFEC mode achieves a throughput of 33.06 Gb/s, an efficiency of 40.35 pJ/b, and a net coding gain of 7.27 dB at 10-6 BER with an inner code BCH (255,223), marking a 1.37-5.2× in throughput and 0.71-2.6 dB gain over prior work.