Reconfigurable Hardware Accelerator for Signal Processing Efficiency
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Solution Overview
Problem
General-purpose processors are inefficient for signal-processing tasks like FFTs, while DSPs are energy-intensive and occupy large silicon area, and fixed digital logic is inflexible.
Innovation Solution
A hardware accelerator with a reconfigurable array of processing elements, direct memory access, and cyclic registers for efficient data buffering and interconnects, enabling flexible and efficient performance of operations like cross-correlation and FFTs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If general-purpose processors are used for signal-processing tasks, then versatility is maintained, but processing speed and energy efficiency deteriorate
Solution Approach 1:
The patent implements a reconfigurable array of processing elements that can be dynamically configured to perform different signal-processing operations. The processing elements can be programmed at runtime to execute specific algorithms such as FFTs, cross-correlations, or other DSP tasks, providing both versatility and high performance. This dynamic reconfiguration allows the system to adapt to different computational requirements while maintaining optimized hardware acceleration for each specific task.
2Productivity
If DSPs are used for signal-processing tasks, then processing speed is improved, but energy consumption and silicon area increase
Solution Approach 1:
The patent divides the processing functionality into multiple independent processing elements arranged in a configurable array. Each processing element performs a specific operation on a portion of the data, allowing the system to process signals in parallel while using minimal resources per element. This segmentation enables high processing speed through parallelism while keeping individual element energy consumption and area small, as each element is relatively simple but many operate simultaneously.
3Productivity
If fixed digital logic is used for signal-processing tasks, then processing speed and energy efficiency are improved, but flexibility deteriorates
Solution Approach 1:
The patent creates a universal processing platform where the same hardware array can be configured to perform multiple different signal-processing functions. The processing elements can be programmed to execute various algorithms including FFTs, cross-correlations, convolutions, and other DSP operations. This multi-functionality is achieved through configurable interconnects and programmable processing elements that maintain optimized hardware acceleration while adapting to different computational tasks.
4Duration of action of stationary object
If data is repeatedly loaded from system memory for processing, then processing continuity is maintained, but processing speed deteriorates due to memory access overhead
Solution Approach 1:
The patent implements data buffers that pre-load and store input data before processing begins. The buffers hold sufficient data to supply the processing elements throughout the entire processing operation, eliminating the need for repeated memory accesses during computation. This preliminary data loading ensures processing continuity while maintaining high speed, as the processing elements can operate continuously on data already resident in the buffers without stalling for memory accesses.
Data Source
AI summary
A hardware accelerator comprises a direct memory access (DMA) system and an array of processing elements (PEs). Each PE comprises two data inputs and two data outputs and can perform a selectable logical or arithmetic operation. The array comprises configurable interconnects for selectively connecting outputs of the PEs to inputs of the PEs. A first data buffer comprises two or more first-edge cyclic registers, for connecting the DMA system to selected data inputs at a first edge of the PE array. A second data buffer comprises two or more second-edge linear or cyclic shift registers, for connecting selected data outputs of a second edge of the PE array to the DMA system.