Reconfigurable Hardware Compiler for Power-Efficient Code Execution
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Solution Overview
Problem
Current tools for compiling high-level software code to hardware require significant modifications and are inefficient in managing power consumption, especially with the shift to multi-core processor architectures where area and performance are less critical, but power efficiency becomes paramount.
Innovation Solution
A reconfigurable hardware architecture and compiler algorithm that allows compiling high-level code directly to hardware without major modifications, using a reconfigurable core with asynchronous datapath and dedicated Load/Store operations, and supporting conditional execution and synchronization to optimize cycle time and reduce silicon area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If high-level code is compiled to hardware using existing tools, then hardware functionality is achieved, but significant code modifications are required
Solution Approach 1:
The patent introduces an intermediate representation (IR) that serves as a mediator between high-level C code and hardware implementation. The compiler translates C code to this intermediate representation, which is then mapped to hardware without requiring modifications to the original high-level code. This intermediate layer enables automatic translation while preserving the simplicity of the source code.
2Ease of manufacture
If code is heavily modified to be transformable by existing tools, then compilation to hardware is enabled, but time-to-market increases
Solution Approach 1:
The patent performs preliminary translation of high-level C code into the intermediate representation during the compilation phase, before hardware implementation is needed. This preliminary action creates a reusable intermediate form that can be directly mapped to hardware, eliminating the need for time-consuming manual modifications and accelerating the time-to-market.
3Adaptability or versatility
If traditional compilation approaches are used, then code transformability is achieved, but power consumption increases
Solution Approach 1:
The patent applies local quality by optimizing specific hardware components based on the intermediate representation. Instead of uniformly implementing all code paths, the compiler analyzes the IR and generates optimized hardware that executes only the necessary operations with appropriate resource allocation. This localized optimization reduces overall power consumption while maintaining code transformability.
Data Source
AI summary
The present invention relates to a method for compiling high-level software code into hardware, transforming each instruction into a respective hardware block and using an execution control signal representing the program pointer for triggering the execution within each respective hardware block.