Reconfigurable HBM Partitioning for Dynamic Processor Channel Mapping
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Solution Overview
Problem
Existing multi-processor systems face limitations in efficiently utilizing high bandwidth memory (HBM) due to static mapping of processor memory channels to HBM bus channels, leading to inefficiencies and performance degradation in certain applications.
Innovation Solution
Implementing a reconfigurable partitioning system that dynamically maps processor memory channels to HBM bus channels using channel and segment multiplexers, allowing flexible allocation of HBM bus segments based on processor needs, thereby enhancing memory access bandwidth and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If static mapping of processor memory channels to HBM bus channels is used, then system simplicity is maintained, but memory access efficiency and bandwidth utilization deteriorate
Solution Approach 1:
The patent implements dynamic mapping of processor memory channels to HBM bus channels through configurable control elements. The first control element dynamically maps processor memory channels to HBM bus channels based on runtime requirements, and the second control element operates subsets of HBM bus channels as independent segments. This dynamic reconfiguration capability allows the system to adapt memory bandwidth allocation to match varying processor needs, thereby improving memory access efficiency without requiring a completely static rigid structure.
Solution Approach 2:
The patent divides the HBM bus into multiple independent segments where subsets of HBM bus channels can be operated as separate entities. The second control element enables independent operation of these segments, allowing different processor cores to access different segments simultaneously. This segmentation increases overall memory bandwidth utilization by enabling parallel access patterns and reducing contention, directly addressing the productivity improvement goal.
2Adaptability or versatility
If dynamic reconfiguration of HBM bus segments is implemented, then adaptability to processor needs is improved, but control system complexity increases
Solution Approach 1:
The patent employs dynamic reconfiguration mechanisms where control elements can change the mapping and segmentation of HBM bus channels at runtime. The first control element dynamically adjusts which processor memory channels are mapped to which HBM bus channels, while the second control element dynamically creates and configures independent bus segments. This dynamic capability provides high adaptability to different processor configurations and workloads.
Solution Approach 2:
The control elements in the patent are designed with multi-functionality, serving multiple purposes: mapping processor channels to bus channels, creating independent segments, and managing resource allocation. This universal design approach allows a single control structure to handle various configuration scenarios, reducing the need for separate dedicated control circuits for each function and thereby managing complexity while maintaining versatility.
3Productivity
If more processor memory channels are supported than HBM bus channels available, then processor capability is utilized, but channel allocation efficiency deteriorates
Solution Approach 1:
The patent implements dynamic mapping that allows processor memory channels to be flexibly assigned to available HBM bus channels based on runtime conditions. When more processor channels are available than physical HBM bus channels, the system dynamically allocates and shares bus channel access among multiple processor channels through the control elements, enabling efficient utilization of both processor capabilities and memory bandwidth.
Solution Approach 2:
The patent enables multiple processor memory channels to be merged or combined to access the same HBM bus channels through time-multiplexed or space-multiplexed allocation. The control elements manage this merging by dynamically assigning groups of processor channels to subsets of HBM bus channels, allowing the system to aggregate processor channel capacity to match available memory bandwidth resources, thereby improving overall channel allocation efficiency.
Data Source
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AI summary
Various example embodiments of a capability for supporting reconfigurable partitioning of high bandwidth memory (HBM) in a multi-processor computing system are presented. The capability for supporting reconfigurable partitioning of HBM in a multi-processor computing system, where the multi-processor computing system includes a multi-processor system-on-chip (SoC) including a set of processors supporting respective sets of processor memory channels and an HBM interconnected via an HBM bus supporting a set of HBM bus channels, may support dynamic mapping of the processor memory channels of the processors of the multi-processor SoC to the HBM bus channels of the HBM, thereby overcoming various limitations of a static mapping of the processor memory channels of the processors of the multi-processor SoC to the HBM bus channels of the HBM. The dynamic processor-to-HBM channel mappings enable mapping of any of the processor memory channels of the processors of the multi-processor SoC to any of the HBM bus channels of the HBM.