Reconfigurable Interconnect for DCNN Power Efficiency

The DCNN processor is divided into multiple independent convolution accelerators (CA0-CA7) that can be individually configured and activated. Each accelerator handles specific convolution operations with dedicated resources (multipliers, accumulators, buffers), allowing the system to segment computational tasks across multiple specialized units rather than using a single general-purpose processor, thereby reducing overall power consumption while maintaining computational capability.

The system employs dynamic reconfiguration capabilities where the convolution accelerators can be programmed at runtime to adapt to different DCNN architectures and computational requirements. The reconfigurable interconnect and control logic allow the hardware architecture to dynamically adjust its data flow paths and operational modes based on the specific neural network being executed, maintaining computational flexibility while optimizing power efficiency for each task.

Each convolution accelerator is equipped with locally dedicated buffers (input buffers, weight buffers, output buffers) that are optimally sized for its specific function. Rather than providing all accelerators with uniformly large memory, the system allocates memory resources locally where they are most needed for each computational unit, reducing total memory area while maintaining the power efficiency benefits of reduced memory traffic.

The memory hierarchy is organized with small, fast, locally dedicated buffers nested within each convolution accelerator, which are in turn nested within the larger processor architecture that includes shared memory resources. This nested structure allows data to be cached locally at the accelerator level for frequently accessed operands, eliminating the need for large centralized memory while minimizing trips to external memory and reducing overall power consumption.

Multiple convolution accelerators are merged into a single integrated processor unit with shared control logic, clock distribution, and interconnect resources. The consolidating of common functions at the processor level while maintaining independent acceleration units allows high-throughput parallel processing without proportionally increasing hardware complexity, as shared resources serve multiple accelerators simultaneously.

The convolution accelerators are designed with universal, reconfigurable components that can handle multiple DCNN operations and data formats. The multipliers and accumulators can be configured for different precision requirements (e.g., 8-bit, 16-bit operations), and the interconnect can dynamically route data between different accelerator combinations, allowing a single hardware design to achieve high performance across various DCNN architectures without requiring separate specialized hardware for each case.