Reconfigurable Interconnect Framework for DCNN Power Efficiency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Deep convolutional neural networks (DCNNs) require significant computational resources and power, making them unsuitable for mobile devices due to their large size and high bandwidth, power, and computing resource demands, which limits their deployment in everyday life, especially in mobile and wearable devices.
Innovation Solution
A hardware accelerator framework is developed, incorporating a reconfigurable dataflow accelerator fabric and a hierarchical memory system, which includes convolution accelerators and digital signal processors (DSPs) to efficiently process convolutional layers, reducing power consumption and memory traffic, and enabling real-time computer vision applications in embedded devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If DCNNs are implemented on conventional hardware platforms, then computational accuracy is improved, but power consumption and device size increase significantly
Solution Approach 1:
The DCNN processor is segmented into multiple independent processing elements (PEs) that can operate in parallel. Each PE handles specific convolution operations, allowing the system to distribute computational load and reduce power consumption per operation while maintaining overall computational accuracy through coordinated parallel processing.
Solution Approach 2:
The patent transitions from conventional two-dimensional GPU architectures to a three-dimensional stacked processor design with multiple processing layers connected via vertical interconnects. This dimensional change enables higher computational density and improved power efficiency by reducing data transfer distances and enabling parallel processing across multiple tiers.
2Measurement precision
If DCNNs are implemented on conventional hardware platforms, then computational accuracy is improved, but device size increases making them unsuitable for mobile devices
Solution Approach 1:
The processor is divided into multiple compact processing elements that can be tightly integrated in a 3D stacked configuration. This segmentation allows the system to achieve high computational power in a smaller footprint by efficiently packing functional units across multiple layers rather than spreading them out in a single large plane.
Solution Approach 2:
The patent employs a nested hierarchical structure where processing elements are organized in layers within a compact 3D stack. Each layer contains multiple PEs that are nested within the overall processor volume, enabling high computational density while minimizing the external device footprint suitable for mobile applications.
3Speed
If high bandwidth is provided to support DCNN operations, then processing speed is improved, but power consumption and complexity increase
Solution Approach 1:
The data bus system is segmented into multiple dedicated channels that connect processing elements to memory and I/O interfaces. This segmentation allows parallel data transfer operations without requiring a single high-bandwidth interface, reducing the complexity of any single bus while achieving aggregate high throughput through coordinated multi-channel operations.
4Adaptability or versatility
If reconfigurable architecture is implemented, then adaptability is improved, but device complexity increases
Solution Approach 1:
The processor implements dynamic reconfiguration capabilities where processing elements can be programmatically configured at runtime to handle different DCNN layer types and operations. This dynamic adaptability allows the same hardware structure to efficiently process various neural network architectures without requiring multiple dedicated hardware designs, balancing versatility with manageable complexity through software-controlled configuration.
Data Source
Figure 1A
Figure 1B
Figure 1C
AI summary
Embodiments are directed towards a method to create a reconfigurable interconnect framework in an integrated circuit. The method includes accessing a configuration template directed toward the reconfigurable interconnect framework, editing parameters of the configuration template, functionally combining the configuration template with a plurality of modules from an IP library to produce a register transfer level (RTL) circuit model, generating at least one automated test-bench function, and generating at least one logic synthesis script. Editing parameters of the configuration template includes confirming a first number of output ports (516) of a reconfigurable stream switch (500) and confirming a second number of input ports (504) of the reconfigurable stream switch. Each output port (516) and each input port (504) has a respective architectural composition. The output port (516) architectural composition is defined by a plurality of N data paths including A data outputs and B control outputs. The input port (504) architectural composition is defined by a plurality of M data paths including A data inputs and B control inputs.