Reconfigurable Interconnect Multiplexer for Flexible Processor Partitioning
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Solution Overview
Problem
Existing server computers have limited flexibility in configuration and are vulnerable to processor failures, which can impact the entire system.
Innovation Solution
The server computer is equipped with multiplexers that can reconfigure interconnect buses dynamically, allowing for flexible partitioning of processors and minimizing the impact of processor failures by isolating faulty components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the server computer uses a fixed processor configuration, then the system design is simple and reliable, but the flexibility in configuration is limited
Solution Approach 1:
The patent implements dynamic reconfiguration of interconnect buses using multiplexers that can switch between different processor partitions based on operational requirements. The system transitions from a static configuration to a dynamic one where the interconnect topology can be reorganized in real-time, allowing the same hardware to adapt to different processing needs without physical reconfiguration
Solution Approach 2:
The interconnect buses are designed to serve multiple functions by connecting to different processor partitions through multiplexers. The same physical bus infrastructure can be dynamically allocated to serve single-processor modes, multi-processor modes, or hybrid modes, making the system universally applicable to various computational scenarios without requiring dedicated hardware for each configuration
2Adaptability or versatility
If the server computer allows dynamic reconfiguration of interconnect buses, then configuration flexibility is improved, but the device complexity increases due to additional multiplexers and control logic
Solution Approach 1:
The processor system is segmented into multiple independent partitions, each capable of operating autonomously. The interconnect buses are also segmented into separate physical buses that can be independently configured and allocated to different partitions. This segmentation allows for granular control and reduces the complexity of managing the entire system as a single unit, as each partition can be configured and managed separately
Solution Approach 2:
Multiplexers are introduced as intermediary devices between the processors and the interconnect buses. These multiplexers act as intelligent switches that route signals between processors and buses based on configuration requirements. By placing multiplexers at the interface level rather than redesigning the entire interconnect fabric, the patent adds reconfiguration capability while minimizing the propagation of complexity throughout the system
3Productivity
If the server computer uses a fixed configuration, then the system is easier to operate, but the ability to maximize interconnect bandwidth is limited
Solution Approach 1:
The system dynamically adjusts interconnect bandwidth allocation based on the operational mode and processing demands. When high bandwidth is required, the multiplexers can be configured to provide direct, low-latency paths between processors. When processors are added or removed, the system automatically reconfigures the interconnect topology to maintain optimal bandwidth utilization without manual intervention
Solution Approach 2:
The system incorporates automatic detection and reconfiguration capabilities that allow it to self-adjust to changes in processor configuration. When processors are added or removed, the system automatically detects the change and reconfigures the interconnect buses to maximize bandwidth utilization, eliminating the need for manual configuration and maintaining operational simplicity while optimizing performance
4Reliability
If the server computer has a fixed processor configuration, then the system structure is simple, but the impact of processor failure on the entire system is greater
Solution Approach 1:
The system is divided into multiple independent processor partitions, each capable of operating autonomously. This segmentation ensures that a failure in one partition does not propagate to other partitions, as the interconnect buses can be reconfigured to isolate the faulty processor. The modular architecture allows the system to maintain functionality with reduced capacity rather than complete failure
Solution Approach 2:
The patent extracts the failure isolation mechanism from the normal operational structure by using multiplexers that can selectively disconnect faulty processors from the interconnect fabric. When a processor failure is detected, the system extracts or removes the faulty processor from the active configuration, preventing it from affecting other processors. This extraction capability is built into the interconnect architecture rather than being a separate emergency system
Data Source
AI summary
A server computer can have multiple potential configurations depending on a state of an input signal. Interconnect buses between processors in a server computer can be reconfigured on startup or dynamically (“hot add/drop”) by one or more multiplexers, thereby allowing the server computer to be flexibly partitioned into custom arrangements of processors, to maximize or change interconnect bandwidth between connected processors in a partition, or to minimize or reduce impact (“blast radius”) due to failed processors or interconnect buses. Each processor can have its own configuration logic to allow partitioning of the server computer as small as a single socket. In an alternative configuration, a common configuration logic can be partitioned and act as separate configuration logics for each partition.