Reconfigurable Interconnect Structure for Low Latency Turbo Mode
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Solution Overview
Problem
Conventional interconnect techniques in high-performance processors fail to adequately address latency and power efficiency in turbo/burst mode operations due to inadequate consideration of RC delay bottlenecks and tunability across voltage-frequency ranges, leading to increased latency and power consumption.
Innovation Solution
The implementation of a reconfigurable interconnect structure with current/voltage-mode drive units, featuring transmission gate circuits and inverters that enable transient current-mode operation, allowing for low overhead and fine-grained control of current/voltage modes to optimize performance and energy efficiency across different voltage, temperature, and process corners.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional current-mode techniques are used to improve interconnect throughput, then energy efficiency is improved, but latency requirements for turbo/burst mode are not met due to complicated data recovery and differential signaling
Solution Approach 1:
The interconnect is segmented into multiple independently controllable lanes, allowing selective activation of current-mode operation only on lanes experiencing congestion or requiring high performance. This segmentation enables the system to achieve current-mode energy efficiency on a per-lane basis while avoiding the latency overhead of full differential signaling across all lanes, thus resolving the contradiction between energy efficiency and latency.
Solution Approach 2:
The system dynamically switches between voltage-mode and current-mode operation based on real-time performance metrics and traffic patterns. During turbo/burst modes when latency is critical, the system transitions to simplified signaling; during normal operation when energy efficiency is prioritized, it employs current-mode techniques. This dynamic adaptability resolves the fixed trade-off between latency and energy efficiency.
2Productivity
If reconfigurable voltage/current-mode operation is implemented, then performance and energy efficiency are optimized across PVT corners, but device complexity increases due to transmission gate circuits and control logic
Solution Approach 1:
The transmission gate circuits are designed to serve multiple functions: they act as switches for mode reconfiguration, as signal routing elements, and as part of the drive strength control mechanism. By making these components multi-functional, the patent reduces the need for separate dedicated circuits for each function, thereby limiting the increase in device complexity while still enabling performance optimization across different operating conditions.
Solution Approach 2:
The system optimizes performance by changing operational parameters (voltage mode vs. current mode, drive strength levels) rather than fundamentally altering the circuit topology. The transmission gates enable parameter changes by selectively connecting different circuit paths, allowing the same physical hardware to operate in multiple modes without requiring completely separate circuit implementations for each mode, thus controlling complexity.
3Loss of time
If transient current-mode operation is used, then delay is reduced and repeater distances are extended, but power consumption increases due to transient current-mode operation
Solution Approach 1:
The system employs periodic or pulsed current-mode operation rather than continuous operation. Current-mode drive is activated only during critical transitions or when signal degradation is detected, and then deactivated when voltage-mode operation suffices. This periodic activation achieves the delay reduction and repeater distance extension benefits of current-mode operation only when necessary, while minimizing overall power consumption by relying on lower-power voltage-mode operation during non-critical periods.
Solution Approach 2:
The patent applies current-mode operation partially - only to the extent necessary to overcome RC delay bottlenecks and extend repeater distances. Rather than using full current-mode operation throughout the entire interconnect, the system applies current-mode enhancement selectively to specific segments or time windows where it provides the most benefit, achieving adequate delay improvement without the excessive power consumption of continuous full-strength current-mode operation.
Data Source
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AI summary
Some embodiments include apparatuses having a first circuit path including drive units coupled in series between a first node and a first additional node, a second circuit path including drive units coupled in series between a second node and a second additional node, each drive unit of the driver units of the first circuit path and the second circuit path including an inverter, and a transmission gate circuit including an input node and an output node coupled to an input node and an output node, respectively, of the inverter; and control circuitry to provide control information to the transmission gate circuit of each of the driver units of the first circuit path and the second circuit path.