Reconfigurable Electrical Interface for Multi-Protocol Avionics Links
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Solution Overview
Problem
The complexity and cost associated with maintaining and updating avionics systems in aircraft are increased due to the need for multiple interface-specific chips and components, which are limited to specific electrical interfaces, making it difficult to accommodate various communication protocols and interfaces.
Innovation Solution
A dynamically reconfigurable electrical interface (DREI) system that includes switches, signal conditioning units, amplifiers, analog-to-digital converters, and processors, allowing for the processing and adaptation of multiple communication protocols by routing and modifying input signals to match different electrical interfaces, thereby enabling flexible communication across various avionics systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated interface-specific chips are used for each communication protocol, then interface reliability is improved, but device complexity and maintenance cost increase
Solution Approach 1:
The patent implements a universal interface chip that can dynamically reconfigure to support multiple communication protocols including ARINC 429, MIL-STD-1553, USB, and Ethernet. The chip contains reconfigurable logic elements and signal conditioning circuits that can be programmed via instruction sets to emulate different interface behaviors, eliminating the need for separate dedicated chips for each protocol while maintaining interface reliability
Solution Approach 2:
The interface chip employs dynamic reconfiguration capability where the hardware logic and signal processing paths can be changed in real-time based on the required communication protocol. The chip transitions from static dedicated interface design to dynamic multi-functional design through programmable logic elements and configurable signal routing, allowing a single chip to adapt to different interface requirements
2Adaptability or versatility
If multiple interface-specific chips are incorporated, then communication protocol compatibility is improved, but ease of manufacture deteriorates
Solution Approach 1:
The patent consolidates support for multiple communication protocols into a single universal interface chip that can be manufactured using standard semiconductor fabrication processes. The chip includes reconfigurable logic blocks and signal conditioning circuits that can be programmed to support ARINC 429, MIL-STD-1553, USB, and Ethernet protocols, simplifying the manufacturing process by eliminating the need to assemble and test multiple different chips
Solution Approach 2:
The interface chip utilizes programmable parameters and configuration registers that allow the same hardware to be configured for different communication protocols. By changing software instruction sets and configuration parameters rather than hardware components, the system achieves protocol compatibility while maintaining consistent manufacturing processes and reducing assembly complexity
3Measurement precision
If interface-specific components are used for each protocol, then signal processing accuracy is improved, but adaptability deteriorates
Solution Approach 1:
The patent implements dynamic signal processing paths within the interface chip that can be reconfigured based on the active communication protocol. Each signal processing chain includes adjustable amplifiers, filters, and conditioning circuits whose parameters can be modified via software control to optimize performance for specific protocols while maintaining accuracy, allowing the same hardware to adapt to different signal characteristics
Data Source
AI summary
A dynamically reconfigurable electrical interface is disclosed that can be used in various applications, including avionics communications. In one embodiment, a first switch receives an input signal and routes it to the applicable signal conditioning path unit that conditions the input signal, after which a second switch routes it to an amplifier. The amplifier provides an amplified signal to an analog-to-digital converter that generates a corresponding numerical value based on the voltage of the amplified signal that is analyzed by a processor to determine information conveyed by the input signal based on a particular electrical interface. Multiple distinct interfaces can be accommodated by on one more processors accessing instructions sets for processing information corresponding to a particular electrical interface. In another embodiment, the processor provides numerical values to a digital-to-analog converter producing an analog signal that is amplified, routed, and conditioned to convey information using a particular electrical interface.