Reconfigurable Interleaver Counters for Multi-Standard Turbo Codes
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing interleavers face challenges in supporting multiple turbo code standards due to high memory requirements for look-up tables and large footprints of dedicated hardware, making it difficult to adapt to new standards and efficient in processing large turbo block sizes.
Innovation Solution
A reconfigurable interleaver using a plurality of counters and memories, where counters are configurable with total count numbers and start values to produce interleaved addresses, allowing for reconfiguration between different interleaving patterns with a small footprint, and utilizing computational elements to operate on retrieved values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a look-up table is used to store interleaving patterns, then multiple interleaving patterns can be supported, but a large amount of memory is needed
Solution Approach 1:
The interleaving pattern generation is divided into multiple independent counters (first counter, second counter, third counter) that can be individually configured. Each counter handles a specific aspect of the interleaving sequence generation, allowing the system to support multiple patterns without storing complete lookup tables by breaking down the complex pattern generation into segmented, reconfigurable components.
Solution Approach 2:
The counters are made reconfigurable with configurable total count numbers and start values, allowing the interleaver to dynamically adapt to different interleaving patterns. This dynamic configuration capability enables the system to switch between multiple standards (UMTS, LTE, etc.) without requiring large static memory storage for all possible patterns.
2Quantity of substance
If dedicated hardware is created for each interleaving standard, then memory usage is reduced, but the device footprint becomes large
Solution Approach 1:
The interleaver uses a universal set of counters and computational elements that can be configured to implement multiple different interleaving standards (UMTS, LTE, and others). Instead of creating dedicated hardware for each standard, the same hardware resources are universally applied across different standards through reconfiguration of counter parameters, significantly reducing the overall device footprint while supporting multiple standards.
3Area of stationary object
If existing hardware is used, then device footprint is minimized, but supporting new standards becomes impossible
Solution Approach 1:
The counters are designed with dynamic reconfiguration capabilities through configurable total count numbers and start values. This dynamic nature allows the hardware to adapt to new interleaving standards as they emerge, maintaining small footprint while ensuring future-proof adaptability. The system can be reconfigured via control signals to support new standards without requiring hardware changes.
4Productivity
If large turbo block sizes are processed, then throughput requirements are met, but computational time and memory needs increase
Solution Approach 1:
The processing of large turbo block sizes is segmented across multiple independent counters that can operate in parallel. The first counter generates base addresses, the second counter applies stride patterns, and the third counter handles additional transformations. This segmentation allows computational work to be divided and executed concurrently, reducing overall computational time while maintaining high throughput for large block sizes.
Data Source
AI summary
A reconfigurable interleaver is provided, configured to produce a sequence of interleaved addresses, configurable for at least two different interleaving patterns. The reconfigurable interleaver comprises a plurality of reconfigurable counters. The number of values that the counters count is configurable as are their start values. The interleaver further comprises a plurality of memory in which the counters indicate memory positions so that values may be retrieved. Computational elements compute an interleaved sequence of addresses in dependency on the retrieved values. By reconfiguring the counters and possibly changing the content of the memories, the interleaver may be configured for a different interleaving pattern.