Reconfigurable ISP Chain Multiplexer for Flexible Image Processing
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Solution Overview
Problem
Existing image processing devices struggle to adapt and optimize image signal processing functions after being embodied as a chip, limiting their ability to accommodate various product applications and image processing results from the same sensor data.
Innovation Solution
An image processing device and chip that includes N ISP functional modules with multiplexers and functional blocks, allowing for the reconstruction of the ISP chain structure and determination of execution order through input and output selection signals, enabling flexible image processing functions such as noise reduction, edge enhancement, and color interpolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the ISP chain structure is fixed after chip embodiment, then the manufacturing process is simplified and reliable, but the adaptability to different product applications is lost
Solution Approach 1:
The patent applies dynamics by making the ISP chain structure reconfigurable through software control. Multiplexers are used to dynamically switch between different functional blocks (denoise, deblur, denoise+deblur) based on application requirements, allowing the fixed physical chip structure to exhibit dynamic functionality without compromising manufacturing reliability.
Solution Approach 2:
The patent implements universality by designing a single chip that can perform multiple image processing functions through configurable functional blocks. The same hardware platform can serve different product applications (mobile phones, tablets, laptops) by changing the ISP chain configuration, eliminating the need for separate chips for each application.
2Adaptability or versatility
If multiple ISP functional blocks are added to provide diverse processing functions, then the adaptability improves, but the device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the image processing system into independent functional blocks (denoise block, deblur block, etc.). Each block can be independently configured and selected, allowing diverse processing functions to be achieved by combining different segments rather than implementing all functions simultaneously in a monolithic structure.
Solution Approach 2:
The patent uses multiplexers as intermediary components to manage the complexity of multiple functional blocks. The multiplexers act as mediators that selectively connect different functional blocks to the signal processing path based on configuration signals, hiding the complexity from the user while providing diverse functions.
3Productivity
If the ISP chain execution order is fixed, then the processing efficiency is optimized for specific applications, but the flexibility to optimize for different applications is lost
Solution Approach 1:
The patent applies parameter changes by allowing the execution order and configuration of functional blocks to be dynamically adjusted through software control. The system can change parameters such as processing sequence, functional block selection, and processing intensity to optimize for different applications while maintaining efficient hardware implementation.
Data Source
AI summary
An image processing device and an ISP chain constructing method are provided which can arbitrarily reconstruct an ISP chain structure. The image processing device is connected to an image sensor, performs a signal process and includes: N (where N is a natural number of equal to or greater than 2) ISP (Image Signal Processing) functional modules that each perform a predetermined image signal process on one, which is determined by an input selection signal, of data output from the image sensor and the other ISP functional modules; and an output module that outputs one, which is determined by an output selection signal, of output data output from the N ISP functional modules as final output data. Accordingly, it is possible to reconstruct an ISP chain even after the ISP chain is embodied as a chip, thereby providing image processing functions optimized for various product applications.