Reconfigurable LDPC Decoder Circuit for Lower Die Area
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Solution Overview
Problem
Existing LDPC decoding systems are expensive in terms of circuitry and die area due to the need for multiple look-up tables and complex architectures, which limits their efficiency and scalability.
Innovation Solution
The implementation of a reconfigurable hardware circuit that shares arithmetic units for both row and column updates, utilizing a single look-up table and dual-port RAM to reduce circuitry and die area, while also enabling simultaneous load/unload functions, allowing for efficient reuse of hardware components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple look-up tables and complex architectures are used for LDPC decoding, then decoding performance is improved, but circuitry cost and die area increase
Solution Approach 1:
The patent implements a reconfigurable hardware circuit that can be dynamically configured to perform multiple functions: row updates, column updates, and load/unload operations. This single multi-functional circuit replaces what would traditionally require separate dedicated circuits for each function, significantly reducing the number of look-up tables and overall die area while maintaining the necessary decoding performance
Solution Approach 2:
The patent employs dynamic reconfiguration of the hardware circuit between different operational modes (row update, column update, load/unload) during the decoding process. This dynamic switching allows the same physical hardware to adapt to different computational requirements at different times, eliminating the need for static multiple dedicated circuits and reducing die area
2Measurement precision
If multiple look-up tables are used for row and column updates, then decoding accuracy is improved, but hardware cost increases
Solution Approach 1:
The reconfigurable hardware circuit serves as a universal computational engine that can perform both row updates and column updates with the same level of precision. By using a single circuit that can be configured for different update types rather than separate dedicated circuits, the patent maintains decoding accuracy while reducing hardware cost and complexity
Solution Approach 2:
The patent changes the operational parameters of the hardware circuit (such as configuration settings, data flow patterns, and computational sequences) to adapt between row update and column update modes. This parameter reconfiguration allows the same hardware to achieve the required decoding accuracy for different operations without requiring separate high-precision circuits for each function
3Adaptability or versatility
If separate hardware is used for row updates and column updates, then functional independence is improved, but circuitry reuse decreases
Solution Approach 1:
The patent implements a dynamically reconfigurable circuit that can switch between row update and column update functions as needed during the iterative decoding process. This dynamic capability provides functional independence when needed while allowing full circuitry reuse across different update types, eliminating the waste of having permanently dedicated separate hardware for each function
Solution Approach 2:
The single reconfigurable hardware circuit is designed to universally handle both row updates and column updates through configuration changes. This universality maximizes circuitry reuse while maintaining the functional independence required for proper LDPC decoding operation, as the circuit can be independently configured for each update type when required
Data Source
AI summary
Various embodiments of the present invention provide systems and circuits that provide for LDPC decoding and/or error correcting. For example, various embodiments of the present invention provide LDPC decoder circuits that include a soft-input memory, a memory unit, and an arithmetic unit. The arithmetic unit includes a hardware circuit that is selectably operable to perform a row update and a column update. In such cases, a substantial portion of the circuitry of the hardware circuit used to perform the row update is re-used to perform the column update.