Reconfigurable Level Shifter Core for Low-Delay Voltage Translation
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Solution Overview
Problem
Existing level shifter circuits that use high voltage devices for interfacing between low and high voltage domains in SoCs suffer from high transient power consumption and propagation delay, which can limit performance due to contention and parasitic capacitance, and are sensitive to process, temperature, and voltage variations.
Innovation Solution
A reconfigurable level shifting core that operates as a current mirror in one mode and a cross-coupled device in another mode, combined with a low voltage control stage and common gate transistors to reduce contention and increase drive strength, allowing for efficient signal propagation between voltage domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If high voltage devices are used in level shifters to interface between low and high voltage domains, then the interface capability is improved, but transient power consumption and propagation delay increase
Solution Approach 1:
The level shifter dynamically reconfigures its operating mode based on signal transition requirements. During steady-state operation, it functions as a high-impedance buffer to minimize power consumption. During signal transitions, it switches to a low-impedance driver mode to provide strong drive capability, thereby reducing transient power consumption while maintaining interface capability.
Solution Approach 2:
The circuit changes its electrical parameters (impedance, drive strength) based on operating conditions. By detecting the transition state and adjusting the operating mode accordingly, the level shifter optimizes the balance between power consumption and signal drive capability, reducing transient power while maintaining interface functionality.
2Adaptability or versatility
If high voltage devices are used in level shifters, then voltage domain interface is improved, but propagation delay increases
Solution Approach 1:
The level shifter dynamically adjusts its drive strength based on the signal transition state. During critical signal transitions, it activates strong drive paths to reduce propagation delay. During steady-state periods, it switches to high-impedance mode to minimize capacitive loading and further reduce delay, thereby optimizing speed while maintaining voltage domain interface capability.
Solution Approach 2:
The circuit prepares the output stage in advance for upcoming transitions by pre-charging or pre-discharging nodes when possible. This preliminary action reduces the effective propagation delay during actual signal transitions, allowing faster switching between voltage domains without sacrificing interface capability.
3Adaptability or versatility
If cross-coupled positive feedback circuits are used for level shifting, then signal propagation between voltage domains is improved, but transient power consumption and propagation delay worsen due to contention and parasitic capacitance
Solution Approach 1:
The patent extracts and eliminates the cross-coupled positive feedback structure that causes contention and parasitic capacitance issues. Instead, it uses a controlled switch-based architecture that provides signal propagation without the harmful interactions of cross-coupled devices, thereby reducing transient power consumption and propagation delay while maintaining signal propagation capability between voltage domains.
Solution Approach 2:
The circuit introduces controlled switches as intermediary elements between the low voltage input and high voltage output. These switches act as mediators that transfer the signal without creating direct contention paths or excessive parasitic capacitance, unlike traditional cross-coupled structures. This intermediary approach reduces harmful effects while maintaining signal propagation.
4Productivity
If level shifters are designed for high performance, then propagation delay and power consumption become limiting factors in SoC
Solution Approach 1:
The level shifter operates in periodic cycles, alternating between low-power buffer mode during steady-state and high-performance driver mode during transitions. This periodic switching between operational states reduces average power consumption while maintaining high performance when needed, preventing power consumption from becoming a limiting factor in SoC design.
Solution Approach 2:
The circuit dynamically adapts its performance characteristics based on operational requirements. By adjusting drive strength and impedance in real-time, it achieves high performance only when necessary, reducing overall power consumption and preventing it from becoming a bottleneck in system-on-chip applications.
Data Source
AI summary
In accordance with an embodiment, a level shifter circuit includes a reconfigurable level shifting core coupled to a first node and a second node. The reconfigurable level shifting core is configured as a current mirror in a first mode, and as a cross-coupled device in a second mode. In the first mode, the current mirror mirrors a current at the first node to the second node, and in the second mode, the cross-coupled device produces a current at the second node in response to a voltage at the first node, and a current at the first node in response to a voltage at the second node.