Reconfigurable Logic Array Instruction Fetch and Transfer
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Solution Overview
Problem
Conventional electronic logic processors face processing delays due to the need for circuitous steps in transferring instructions and resources, limiting their ability to efficiently and flexibly execute computational and data processing tasks.
Innovation Solution
A configurable computer system with a logical processor array that includes reconfigurable logic elements, allowing for external modification without clocking or synchronization, and a memory system with instructions containing fetch and transfer configuration data to direct the processor on where and how to locate, read, and generate succeeding instructions, enabling the execution of multiple prior art instructions simultaneously.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional electronic logic processors use dedicated ALU with register file and sequential instruction execution, then the processor can perform computations, but processing delays are introduced due to circuitous steps in transferring instructions and resources
Solution Approach 1:
The patent merges the ALU, register file, and memory into a unified reconfigurable logic array where computation and storage are integrated. This eliminates the need for data to travel between separate components (memory→register file→ALU→register file→memory), reducing processing delays by allowing direct access and computation within the same reconfigurable fabric.
Solution Approach 2:
The patent employs dynamically reconfigurable logic elements that can change their function and connectivity based on the task at hand. This dynamic reconfiguration allows the processor to optimize the data path for each specific operation, eliminating fixed circuitous routes and enabling direct computation paths that reduce processing time.
2Productivity
If prior art processors execute one instruction at a time with multiple clock cycles, then instruction execution is precise, but the processor cannot efficiently execute multiple instructions simultaneously
Solution Approach 1:
The patent segments the instruction stream into multiple parallel execution units within the reconfigurable logic array. Each segment can be processed simultaneously by different logic elements, enabling one instruction to execute the equivalent of dozens or hundreds of prior art instructions in parallel, thereby increasing throughput without proportionally increasing external control complexity.
Solution Approach 2:
The reconfigurable logic elements serve multiple functions: they can act as computation units, storage elements, or data routing switches depending on the configuration. This multi-functionality allows a single unified array to handle diverse computational tasks simultaneously, eliminating the need for separate dedicated hardware for each function and enabling efficient parallel instruction execution.
3Speed
If memory is directly connected to ALU in early computer architectures, then data access is fast, but such connectivity is substantially impractical in modern architectures
Solution Approach 1:
The patent nests the register file functionality within the reconfigurable logic array itself, rather than having it as a separate external component. The logic elements can be configured to store and retrieve data locally, effectively nesting storage capabilities within the computation fabric. This eliminates the need for complex external memory interfaces while maintaining fast data access, as data resides within the same reconfigurable structure.
Data Source
AI summary
A method and system are provided for configurable computation and data processing. A logical processor includes an array of logic elements. The processor may be a combinatorial circuit that can be applied to modify computational aspects of an array of reconfigurable circuits. A memory stores a plurality of instructions, each instruction including an instruction-fetch data portion and an output data transfer data portion. One or more memory controllers are coupled to the memory and receive instructions and/or output data from the memory. A back buffer is coupled with the memory controller and receives instructions from the memory controller. The back buffer sequentially asserts each received instruction upon one or more memory controllers. The memory controllers transfer data received from the memory to a target, such as an array of reconfigurable logic circuits that are optionally coupled to the memory, the back buffer, and one or more additional memory controllers.