Reconfigurable Logic Circuit With Fast Configuration Bit Switching
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Solution Overview
Problem
Conventional reconfigurable logical circuits require millisecond-order periods for overall rewriting, making it difficult to achieve desired performance, especially in operations that require real-time rewriting, as the rewrite period is often longer than the processing period, leading to inefficient processing and performance deterioration.
Innovation Solution
A reconfigurable logical circuit with a data processing unit, a memory storing multiple combinations of configuration control bits, and a selector unit that rapidly switches between these combinations to reconfigure processing contents, allowing for rewrite periods of 1 ms or shorter by determining switching timing through software control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional reconfiguration method using external clock and control signals is used, then the logical circuit can be reconfigured, but the rewrite period becomes millisecond-order which is too long for real-time processing
Solution Approach 1:
The patent segments the configuration control bits into multiple groups that can be independently selected and rewritten. Instead of rewriting the entire configuration at once, only the necessary configuration groups are updated, significantly reducing the rewrite period while maintaining full reconfiguration capability.
Solution Approach 2:
The patent pre-prepares multiple sets of configuration control bits in advance within the logical circuit's internal memory. When reconfiguration is needed, the system simply switches between pre-prepared configuration sets rather than generating configurations in real-time, enabling nanosecond-order switching without complex external control.
2Adaptability or versatility
If overall rewrite of the logical circuit is performed, then the processing contents can be completely changed, but the rewrite period becomes excessively long compared to the processing period
Solution Approach 1:
The configuration space is divided into multiple independent configuration groups, each controlling different functional aspects of the logical circuit. This allows selective rewriting of only the necessary groups rather than performing complete overall rewrite, thereby maintaining processing content change capability while dramatically improving processing efficiency.
Solution Approach 2:
The patent implements partial rewriting by updating only the specific configuration groups that need to change, rather than performing excessive full-circuit rewriting. This partial action approach maintains the ability to completely change processing contents when needed, while avoiding the productivity loss associated with unnecessary rewriting of unchanged configuration groups.
3Loss of time
If partial rewrite is performed instead of overall rewrite, then the rewrite period is reduced, but even partial rewrite takes considerable period when large functional blocks are rewritten
Solution Approach 1:
The patent segments configuration control bits into finely-grained groups that can be independently managed and rewritten. This segmentation enables the system to rewrite only the smallest necessary configuration units, minimizing rewrite period even when large functional blocks need to be reconfigured, while the internal management structure handles the complexity automatically.
Solution Approach 2:
The patent introduces an internal configuration management mechanism that acts as an intermediary between the reconfiguration request and the actual configuration bits. This intermediary automatically manages the complexity of partial rewriting by determining which configuration groups need to be updated, eliminating the need for external complex configuration management while achieving fast partial rewriting.
Data Source
AI summary
A reconfigurable logical circuit includes a data processing unit; a memory in which plural combinations of configuration control bits are stored; and a selector unit that selectively switches the plural combinations of configuration control bits stored in the memory and supplies a selected one of the plural combinations of configuration control bits to the data processing unit to reconfigure processing contents of the data processing unit.