Reconfigurable MAC Column Architecture for Flexible IC Algorithms
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing integrated circuits with prefabricated basic structures lack sufficient flexibility in configurability, despite meeting requirements for small area requirements, low power consumption, and low costs, failing to adapt to changing application needs.
Innovation Solution
The circuit architecture allows for adaptable interconnections between arithmetic and control units, specifically designed for groups of functions or algorithms, enabling dynamic configuration and simultaneous execution of multiple algorithms, with optional integration of microprocessors for enhanced flexibility and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If prefabricated basic structures are used in integrated circuits, then area requirements, power consumption, and manufacturing costs are reduced, but configurability and flexibility are insufficient
Solution Approach 1:
The circuit is divided into multiple columns, each containing a sequence of arithmetic units and selection units. This segmentation allows independent configuration of each column while maintaining overall system flexibility, resolving the contradiction between prefabricated structure efficiency and configurability needs.
Solution Approach 2:
Selection units are introduced that can dynamically connect arithmetic units in different configurations. These selection units enable the circuit to adapt its structure at runtime, providing the needed configurability while maintaining the efficiency of prefabricated basic structures.
2Adaptability or versatility
If user-programmable components are used to increase flexibility, then adaptability to changing requirements improves, but area requirements, power consumption, and costs increase
Solution Approach 1:
The arithmetic units are designed to perform multiple functions through different connection configurations. The same physical hardware can execute different algorithms by reconfiguring the selection units, providing universal functionality without requiring additional dedicated circuits for each function, thus avoiding increased power consumption.
Solution Approach 2:
Instead of creating multiple dedicated hardware copies for different functions, the patent uses a single set of arithmetic units that can be reconfigured through selection units. This virtual copying through reconfiguration provides flexibility without the power overhead of multiple physical copies.
3Adaptability or versatility
If fully configurable designs are implemented, then user flexibility and adaptability are maximized, but manufacturing complexity and costs significantly increase
Solution Approach 1:
The circuit is organized into standardized columns with repeating patterns of arithmetic units and selection units. This segmentation enables modular manufacturing where each column can be produced using the same prefabricated structures, significantly reducing manufacturing complexity while maintaining full configurability through the selection units.
Solution Approach 2:
The patent uses parameterized designs where the same basic structural units are instantiated with different parameters to create customized circuits. This approach allows fully configurable designs to be manufactured using standard processes, as the complexity is managed through parameter variation rather than structural variation.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
The invention relates to a circuit architecture for an integrated circuit with the following features: - at least one group (G) with several computing units (MAC) arranged in columns (S), - in the columns (S) at inputs (e) of several computing units (MAC) a single first selection unit (MUX) is connected upstream of each, wherein no other selection unit (MUX) is connected directly upstream of this selection unit (MUX).- The first selection units (MUX) are coupled to each other in such a way that a horizontal and/or vertical linking of the processing units (MAC) within a group (G) and/or a linking of processing units (MAC) to an upstream group (G) is possible, - second selection units (TS) are each connected downstream of a column (S) of processing units (MAC), - the second selection units (TS) of a group (G) are connected on the output side to a bus line (L), - a microprocessor (uP) is coupled to this bus line (L).