Reconfigurable MAC Pipelines With Switchable Memory Roles
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Solution Overview
Problem
Existing multiplier-accumulator circuitry in integrated circuits lacks flexibility and efficiency in performing multiply and accumulate operations, as they are not easily reconfigurable to meet changing system requirements, leading to suboptimal performance in terms of speed and resource utilization.
Innovation Solution
The integration of a plurality of separate multiplier-accumulator circuits with shadow registers and a switch interconnect network in a field programmable gate array (FPGA) allows for pipelining and concatenation of operations, enabling dynamic reconfiguration of the number of interconnected circuits to optimize performance based on temporal requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If multiplier-accumulator circuits are made fixed and simple in structure, then device complexity is reduced, but adaptability to changing system requirements deteriorates
Solution Approach 1:
The patent implements dynamic reconfigurability by organizing multiplier-accumulator circuits into rows that can be selectively connected or disconnected through control logic. This allows the system to transition between different operational states (e.g., concatenated mode for high performance vs. independent mode for flexibility) based on temporal requirements, resolving the contradiction between structural simplicity and adaptability.
Solution Approach 2:
The circuit is divided into multiple independent rows of multiplier-accumulator circuits, each capable of operating autonomously or being concatenated with others. This segmentation enables selective activation and connection of circuit rows, providing adaptability without requiring complete redesign of the entire circuit structure.
2Productivity
If the number of interconnected multiplier-accumulator circuits is increased to improve speed, then productivity increases, but device complexity increases
Solution Approach 1:
The system dynamically adjusts the number of interconnected circuits based on performance requirements. Control logic enables or disables connection between circuit rows, allowing the system to scale from single-circuit operation to multi-circuit concatenation. This dynamic adjustment achieves high productivity when needed while maintaining simpler operational modes when full performance is not required.
Solution Approach 2:
Each multiplier-accumulator circuit row is designed with universal interfaces and control mechanisms that enable them to function both independently and in concatenated configurations. The same hardware structure serves multiple purposes: standalone operation for simple tasks and interconnected operation for high-performance applications, eliminating the need for separate circuit designs for different performance levels.
3Adaptability or versatility
If reconfiguration capability is added to meet changing requirements, then adaptability improves, but device complexity increases
Solution Approach 1:
The control mechanism is segmented to match the physical segmentation of circuit rows. Each row has associated control logic that can independently enable or disable connections, allowing granular reconfiguration without requiring a centralized complex control system. This distributed control approach reduces overall complexity while maintaining full reconfigurability.
Solution Approach 2:
The circuit includes pre-configured connection interfaces and control mechanisms that are prepared in advance for various operational modes. The ability to concatenate or disconnect rows is built into the fundamental structure, eliminating the need for complex runtime reconfiguration logic and reducing the complexity of the control system.
Data Source
AI summary
An integrated circuit including configurable multiplier-accumulator circuitry, wherein, during processing operations, a plurality of the multiplier-accumulator circuits are serially connected into pipelines to perform concatenated multiply and accumulate operations. The integrated circuit includes a first memory and a second memory, and a switch interconnect network, including configurable multiplexers arranged in a plurality of switch matrices. The first and second memories are configurable as either a dedicated read memory or a dedicated write memory and connected to a given pipeline, via the switch interconnect network, during a processing operation performed thereby; wherein, during a first processing operations, the first memory is dedicated to write data to a first pipeline and the second memory is dedicated to read data therefrom and, during a second processing operation, the first memory is dedicated to read data from a second pipeline and the second memory is dedicated to write data thereto.