Reconfigurable Processor Matrix Read Circuit
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Solution Overview
Problem
Existing reconfigurable processors face inefficiencies in accessing matrices due to the need for multiple read steps when converting between row major and column major formats, especially with varying data types and bit widths, which slows down matrix computations.
Innovation Solution
A reconfigurable processor with a configurable circuit that includes dual read ports for parallel normal and transpose reads, utilizing a memory array with slots of multiple data widths and a reshape circuit for efficient data transformation, allowing simultaneous row major and column major vector access without throughput loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple read steps are used to convert between row major and column major formats, then matrix access flexibility is improved, but access time increases
Solution Approach 1:
The patent pre-organizes matrix data in memory with a specific layout that enables both row-major and column-major access patterns. The memory is configured with banks and word lines arranged so that both read directions can access data directly without requiring conversion steps, thus performing the transformation action in advance during memory organization rather than during data access
Solution Approach 2:
The patent introduces a new dimension of memory organization by using multiple memory banks with specific interconnections. Instead of using a single memory structure optimized for one access pattern, the invention creates a multi-dimensional memory architecture where data can be accessed along different dimensions (row or column) simultaneously, bypassing the need for format conversion
2Adaptability or versatility
If data width is varied for different configurations, then processing versatility is improved, but access complexity increases
Solution Approach 1:
The patent creates a universal memory access interface that can handle multiple data widths (8-bit, 16-bit, 32-bit) through the same structural organization. The memory banks and read ports are designed with configurable width parameters that allow the same physical structure to serve multiple data type requirements, thus achieving multi-functionality without proportionally increasing access complexity
Solution Approach 2:
The patent enables dynamic configuration of memory access parameters including data width, bank selection, and word line configuration. By allowing these parameters to be changed through configuration registers or control signals, the system can adapt to different data types and access patterns without physical reconfiguration, managing complexity through software-controlled parameter adjustment
3Productivity
If parallel read ports are added for simultaneous normal and transpose reads, then throughput is improved, but device complexity increases
Solution Approach 1:
The patent divides the memory into multiple independent banks, each with its own read port and control logic. This segmentation allows parallel access to different portions of the matrix simultaneously - one port performing normal reads while another performs transpose reads. The segmentation isolates the complexity into manageable units rather than requiring a single complex unified interface
Solution Approach 2:
The patent merges multiple read ports and their associated logic into a unified memory structure that shares common resources such as word lines, bit lines, and control signals. By combining these elements rather than implementing completely separate memory structures, the patent achieves parallel read capability while reducing overall device complexity through resource sharing
Data Source
AI summary
A configurable circuit configurable according to the data width of elements of a matrix is described that includes a memory array, logic to write a matrix to the memory array having elements with a data width which can be specified using configuration data, logic for a transpose read of the matrix as-written and logic for normal read of the matrix as-written. The memory array includes first and second read ports operable in parallel. Transpose read logic and normal read logic can be coupled to the first and second read ports, respectively, allowing transpose and normal read of a matrix simultaneously.