Reconfigurable IC Memory Arrays for Dynamic Cache Configuration
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Solution Overview
Problem
Existing integrated circuit (IC) die products have limited variability in cache characteristics, leading to inefficiencies in production and marketing, as different IC dies within a family have distinct cache requirements, necessitating the production of both small and large cache IC dies.
Innovation Solution
An IC die is designed to be reconfigurable, allowing it to selectively operate its memory arrays as either cache arrays, tag arrays, or state arrays based on the availability of other IC dies, enabling flexible configuration during manufacturing, assembly, boot-up, or runtime to meet varying cache requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If IC dies are designed with fixed cache characteristics, then manufacturing is simpler, but adaptability to different applications is reduced
Solution Approach 1:
The patent applies dynamics by enabling the memory arrays to change their function dynamically. The IC die can reconfigure its memory arrays from fixed cache/tag array roles to flexible configurations based on operational needs, allowing adaptation to different cache requirements without physical redesign
Solution Approach 2:
The patent implements universality by designing memory arrays that can serve multiple functions. The same physical memory arrays can operate as cache arrays, tag arrays, or state arrays depending on configuration, making the IC die versatile for different applications and cache hierarchies
2Adaptability or versatility
If multiple IC die variants with different cache sizes are produced, then specific cache requirements are met, but production complexity and inventory requirements increase
Solution Approach 1:
Instead of manufacturing multiple specialized variants, the patent creates a universal IC die design where memory arrays can be configured for different cache requirements through software or configuration controls, eliminating the need for physical variant production
Solution Approach 2:
The patent changes operational parameters rather than physical structure. By modifying configuration parameters, addressing modes, and memory array assignments, the system adapts to different cache sizes and hierarchies from a single standardized hardware design
3Adaptability or versatility
If memory arrays are dedicated to single functions, then performance is optimized for that function, but flexibility is reduced
Solution Approach 1:
The system dynamically assigns functions to memory arrays based on operational context. The cache controller can reallocate arrays between cache, tag, and state functions as needed, maintaining performance through adaptive configuration rather than fixed dedicated assignments
Data Source
AI summary
Techniques and mechanisms for selectively configuring an integrated circuit (IC) chip to provide tag array functionality and/or cache array functionality. In an embodiment, an IC chip comprises a first array of memory cells, a second array of memory cells, and a cache controller. Based on whether the IC chip is coupled to another IC chip, selector circuitry of the IC chip configures one of multiple possible modes of the cache controller. A first mode of the multiple modes is to provide tag array functionality with the first array, and cache array functionality with the second memory cell array. A second mode of the multiple modes is to provide tag array functionality with the second memory cell array, and cache array functionality with a remote array of memory cells. In another embodiment, the cache controller is reconfigured to another mode based on a change to a power consumption characteristic.