Reconfigurable On-Chip Memory Bank Runtime Adaptation
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Solution Overview
Problem
Current on-chip memory systems have a fixed memory composition ratio, leading to inefficiencies in memory utilization for varying calculation tasks in artificial intelligence processing cores.
Innovation Solution
A reconfigurable on-chip memory bank that includes a cell array, data path units, and a bank controller capable of determining data paths and address systems at runtime to optimize memory utilization based on task characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a fixed memory composition ratio is used in on-chip memory, then the memory structure is simple and easy to manufacture, but memory utilization efficiency deteriorates for varying calculation tasks
Solution Approach 1:
The patent implements a reconfigurable on-chip memory bank that can dynamically change its configuration during runtime. The memory composition ratio between scratch pad and shared memory can be adjusted based on the characteristics of calculation tasks, transforming a static memory structure into a dynamic one that adapts to different workloads while maintaining manufacturing simplicity through a unified physical structure.
Solution Approach 2:
The patent changes the parameter of memory composition ratio from fixed to variable. By allowing the ratio of scratch pad to shared memory to be reconfigured based on task characteristics, the system optimizes memory utilization efficiency without complicating the manufacturing process, as the same physical memory structure supports multiple configuration states.
2Device complexity
If a fixed memory composition ratio is used in on-chip memory, then the device complexity is low, but adaptability to different calculation tasks deteriorates
Solution Approach 1:
The patent introduces dynamic reconfiguration capability to the memory system. The memory bank can switch between different composition ratios of scratch pad and shared memory based on the characteristics of assigned calculation tasks, enabling a single memory structure to adapt to varying workloads without increasing device complexity.
Solution Approach 2:
The patent makes the on-chip memory bank universal by enabling it to serve different functions through reconfiguration. The same physical memory structure can be configured with different scratch pad to shared memory ratios to optimize for different calculation task types, achieving multi-functionality without additional hardware complexity.
3Productivity
If reconfigurable memory composition is implemented, then memory utilization efficiency is improved, but device complexity increases
Solution Approach 1:
The patent implements dynamic reconfiguration of the memory bank's composition ratio during runtime based on task characteristics. This allows the system to optimize memory utilization efficiency for different calculation tasks while managing device complexity through a controlled reconfiguration mechanism that adjusts the scratch pad to shared memory ratio without requiring complete hardware redesign.
Data Source
AI summary
A reconfigurable on-chip memory bank, reconfigurable on-chip memory, system-on-chip having same mounted thereon, and method for using reconfigurable on-chip memory is provided. The reconfigurable on-chip memory bank comprises a cell array in which a plurality of cells are arranged and data are stored, a first path unit configured to move data in the cell array, a second path unit configured to move data in the cell array and a bank controller operably coupled with the first and second path units, and configured to determine, according to a path control signal during runtime, data path which data are to be transmitted to or received from, to use a first address system when the first path unit is determined to be the data path, and to use a second address system different from the first address system when the second path unit is determined to be the data path.